JPS604268A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS604268A JPS604268A JP58112009A JP11200983A JPS604268A JP S604268 A JPS604268 A JP S604268A JP 58112009 A JP58112009 A JP 58112009A JP 11200983 A JP11200983 A JP 11200983A JP S604268 A JPS604268 A JP S604268A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- source
- temporary
- present
- semiconductor equipment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/80—FETs having rectifying junction gate electrodes
Landscapes
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は半導体装置、特に電界効果トランジスタの構造
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of semiconductor devices, particularly field effect transistors.
電界効果トランジスタ、例えばＧａＡｓＦＥＴではゲー
ト−ソース間の直列抵抗を減らす工夫が行なわれている
。例えば、ゲート電極をＧ ａ Ａ ｓ基板の四部に設
けるリセスゲート型Ｊｉ”ｌｌＴや、ゲート電極をソー
ス側寄りに形成したＦ ＋Ｄ Ｔ等が提案されている。In field effect transistors, such as GaAsFETs, efforts have been made to reduce the series resistance between the gate and source. For example, a recessed gate type Ji''llT in which the gate electrode is provided on four parts of the GaAs substrate, and an F+D T in which the gate electrode is formed closer to the source side have been proposed.
しかしながら、そのだめの製法が難しいため製造面での
不都合が多く、効率よく生産されていないのが現状であ
る。However, because the method for producing this product is difficult, there are many inconveniences in manufacturing, and the current situation is that it is not efficiently produced.
本発明は構造的に新規な）ｉ’Ｅ３Ｔｉｉ出し、かつ製
法においても容易に案出□した構造のＦ’ｌＪＴか得ら
れるようにしだもので、ソース側からドレイン側に向か
つ−Ｃ傾斜するように学畔ヰ＃衾ソースおよびドレイン
領域を設け、この間にあってかつソース寄りに位置する
ようにゲート電極を設けた（）ａＡｓＦＥＴが本発明の
ＦＥＴである。The present invention is designed to obtain an F'lJT which is structurally novel and which is easily devised in terms of manufacturing method. The FET of the present invention is an AsFET in which source and drain regions are provided, and a gate electrode is provided between these regions and located closer to the source.
以下に本発明の一実施例を図１１ｎを用いて説明する。An embodiment of the present invention will be described below using FIG. 11n.
先ず第１図（ａ）に示す様に半絶嫌性（＋ ａ Ａ ｓ
ｇ板１にＳｉ等のＮ型不純物ケ用い、加速エネルギー３
０ＫｅＶ 〜１５０ＫｅＶ、ドーズ量１ ｘ １０”ｃ
ｍ” 〜１×１０１３ｃＩｒＬ−２イオン注入を行いＮ
型能動層２を形成する。次に第１図（ｂ）に示す様に化
学気相成長法をＳｉＮをアニール保護膜３として形成す
る。次に、第１図（Ｃ）に示す様にＡ／、ＭＯ等の金属
を用いたゲート巾０．２μｎ〜２μｎ、厚さ数千への仮
ゲート４の形成を行う。次に第１図ｔｄｌに示す様に化
学気相成長法を用いて仮ゲートメタルを被覆する厚さ数
千にのＳｉＯ會又は５ｉＮ）ｌ’Ａ５を形成し、その後
ＣＦ、等のエツチングガスを用いた全面１（、Ｔ Ｅに
より第１図（ｅ）に示す様な仮ゲートメタルの側壁部に
５ｉ０２又はＳ ｒ Ｎ ｌ罠が残る様な加工ｒ行う。First, as shown in Figure 1 (a), semi-absolute aversion (+ a A s
N-type impurities such as Si are used in the g-plate 1, acceleration energy 3
0KeV to 150KeV, dose 1 x 10”c
m”~1×1013cIrL-2 ion implantation was performed and N
A mold active layer 2 is formed. Next, as shown in FIG. 1(b), SiN is formed as an annealing protective film 3 by chemical vapor deposition. Next, as shown in FIG. 1C, a temporary gate 4 is formed using a metal such as A/M0 or the like to have a gate width of 0.2 μm to 2 μm and a thickness of several thousand. Next, as shown in Figure 1 (tdl), a SiO film or 5iN)l'A5 with a thickness of several thousand is formed to cover the temporary gate metal using chemical vapor deposition, and then an etching gas such as CF is applied. The entire surface 1 (1) used is processed so that 5i02 or S r N l traps remain on the side wall portion of the temporary gate metal as shown in FIG. 1(e) using TE.
次に第１図（ｆ）にスフとして、加速エネルギ−１００
Ｋｅ Ｖ 〜３００ＫｅＶドース耽１ ｘ １０１３ｃ
ｍ−２〜ｓ ｘ １０１４ｃｍ ” 、注入角度３０度
〜７０度の斜め方向よりのイオン注入によりＮ”Ｉ端６
の形成全行う。ここで斜め方向とはＧ ａ Ａ ５Ｍｇ
５ ｉ；’ｚｒのノース側が仮ゲートとの距離が近づく
様な方向すなわちソースからドレインに傾斜する方向に
選ぶ。次に第１図ｔｇ）〜ｔｉ）に示す様にでらに化学
気相成長法を用いて数千への厚さの５ｉｎ２又は５ｉＮ
ｌｌ罠７を成長し、その後Ｐルレジスト膜８を全面に塗
布し、しかる後ＣＪｉ”４等のエツチングガスを用いて
ＢＴＢを行い凸部となる仮ゲートメタルの頭出しを行う
。次に第１図（ｊ）に示す様に仮ケートメタルを除去し
た後、７５０°Ｃ〜８５０℃、Ｈ２又はＮ２雰囲気中で
アニールを行い、Ｎ型ｅ ａｈ ｒ＝及びＮ＋層の活性
化を行う。次に、第１図（ｋ）に示す様に仮ゲートメタ
ル下部のＳ ｉ ０２１１ｕ又はＳ ｉ Ｎ Ｉｓの開
口を行い、しかる後ゲートメタル９を形成する。Next, as shown in Fig. 1(f), the acceleration energy -100
Ke V ~300KeV dose 1 x 1013c
m-2~s x 1014cm'', N''I end 6 by oblique ion implantation with an implantation angle of 30 degrees to 70 degrees.
The entire formation is done. Here, the diagonal direction is G a A 5Mg
5 i;' Select a direction in which the north side of zr is closer to the temporary gate, that is, a direction inclined from the source to the drain. Next, as shown in FIG.
After growing the ll trap 7, a P resist film 8 is applied to the entire surface, and then BTB is performed using an etching gas such as CJi'' 4 to locate the beginning of the temporary gate metal that will become the convex part. As shown in Figure (j), after removing the temporary metal, annealing is performed at 750°C to 850°C in a H2 or N2 atmosphere to activate the N-type e ah r= and N+ layers.Next, , as shown in FIG. 1(k), an opening is made in S i 0211u or S i N Is under the temporary gate metal, and then gate metal 9 is formed.
本発明の製法によるＧａＡ ｓ ｈ４Ｅｓ ＦＩＢＴの
完成断面図を第２図に示す。FIG. 2 shows a completed sectional view of a GaA s h4Es FIBT produced by the manufacturing method of the present invention.
本発明の製造方法による０ａＡｓ ＭＥＳ ＦＥＴはソ
ース側のＮ＋層かゲートに近接し、ドレイン側のＮ＋層
が仮ゲート側壁の厚さによって、ゲートより必然的に離
れて形成される構造となる。従って、ゲート−ドレイン
耐圧の低下をもたらすことなく、ソース抵抗の低減をは
かることができ、従来得られなかっだＦ ｇ Ｔの特性
向上が達成できる。The 0aAs MES FET manufactured by the manufacturing method of the present invention has a structure in which the N+ layer on the source side is close to the gate, and the N+ layer on the drain side is necessarily formed apart from the gate depending on the thickness of the temporary gate sidewall. Therefore, it is possible to reduce the source resistance without reducing the gate-drain breakdown voltage, and it is possible to achieve an improvement in the characteristics of F g T that could not be obtained conventionally.
なお、ゲートをリセス構造にしてもよい。Note that the gate may have a recessed structure.
第１図（ａ）乃至＋ｋ）は本発明の一実施例による各工
程での断面図、第２回は本発明によるＧａＡｓ ＭＥＳ
ＦｇＴの構造断面図を示す。
１・・・・・・Ｇ ａ Ａ ｓ半絶縁基板、２・・・・
・・イオン注入能動層、３・・・・・・アニール保護膜
、４・・・・・・仮ゲートメ′タル、５・・・・・・８
ｉ０２ ｏｒ ＳｉＮ （側壁膜）、６・・・・・・Ｎ
＋イオン注入層、７・・・・・・Ｓ ｉＯ２ｏｒ ８
ｉＮ膜、８・・・・・・レジスト族、９・・・・・・ゲ
ートメタル、１０・・・・・・ソース電極、ｌｌ・・・
・・・ドレイン電極。
代理人 弁理士 内 原 晋（１）、’、）、：ｆｆ−
″）冥 ／ 図
外 ２ 図Figures 1 (a) to +k) are cross-sectional views at each step according to an embodiment of the present invention, and the second figure is a GaAs MES according to the present invention.
A cross-sectional view of the structure of FgT is shown. 1...G a As semi-insulating substrate, 2...
...Ion implantation active layer, 3...Annealing protective film, 4...Temporary gate metal, 5...8
i02 or SiN (side wall film), 6...N
+Ion implantation layer, 7...S iO2or 8
iN film, 8...resist group, 9...gate metal, 10...source electrode, ll...
...Drain electrode. Agent Patent Attorney Susumu Uchihara (1),',),:ff-
″）Mei / Outside the figure 2 figure
Claims (1)
ース側からドレイン側へ傾斜するように設けられ、かつ
その間にあってソース寄りにゲート電極が形成されたこ
とを％徴とする半導体装置。A semiconductor device characterized in that a semiconductor impurity layer serving as a source and a drain region is provided so as to be inclined from the source side to the drain side, and a gate electrode is formed between them toward the source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58112009A JPS604268A (en) | 1983-06-22 | 1983-06-22 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58112009A JPS604268A (en) | 1983-06-22 | 1983-06-22 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS604268A true JPS604268A (en) | 1985-01-10 |
Family
ID=14575677
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58112009A Pending JPS604268A (en) | 1983-06-22 | 1983-06-22 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS604268A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5296728A (en) * | 1990-02-26 | 1994-03-22 | Rohm Co., Ltd. | Compound semiconductor device with different gate-source and gate-drain spacings |
| US5614739A (en) * | 1995-06-02 | 1997-03-25 | Motorola | HIGFET and method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57210675A (en) * | 1981-06-18 | 1982-12-24 | Matsushita Electric Ind Co Ltd | Manufacture of field effect transistor |
-
1983
- 1983-06-22 JP JP58112009A patent/JPS604268A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57210675A (en) * | 1981-06-18 | 1982-12-24 | Matsushita Electric Ind Co Ltd | Manufacture of field effect transistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5296728A (en) * | 1990-02-26 | 1994-03-22 | Rohm Co., Ltd. | Compound semiconductor device with different gate-source and gate-drain spacings |
| US5614739A (en) * | 1995-06-02 | 1997-03-25 | Motorola | HIGFET and method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS5950567A (en) | Manufacture of field effect transistor | |
| JPH0571134B2 (en) | ||
| JPS604268A (en) | semiconductor equipment | |
| US4053917A (en) | Drain source protected MNOS transistor and method of manufacture | |
| JPS61248570A (en) | Mesfet device and manufacture thereof | |
| JPS6252957B2 (en) | ||
| JPS62115781A (en) | field effect transistor | |
| JPS63208275A (en) | field effect transistor | |
| JP3106747B2 (en) | Method for manufacturing compound semiconductor FET | |
| JPS5935479A (en) | Manufacture of semiconductor device | |
| JP3176835B2 (en) | Method of forming compound semiconductor device | |
| JP2726730B2 (en) | Manufacturing method of field effect transistor | |
| JPS5832508B2 (en) | Transistor | |
| JPS62190768A (en) | Semiconductor device | |
| JPH05291294A (en) | Manufacture of thin film transistor | |
| JPS61265870A (en) | Method for manufacturing field effect transistors | |
| JPS6347982A (en) | Semiconductor device | |
| JPH05267350A (en) | Method for manufacturing semiconductor device | |
| JPS62232971A (en) | Manufacture of semiconductor transistor | |
| JPS6050966A (en) | Manufacture of field effect transistor | |
| JPH05206461A (en) | Manufacture of semiconductor device | |
| JPS5896732A (en) | Ion implantation | |
| JPH05152281A (en) | Semiconductor device | |
| JPH0523496B2 (en) | ||
| JPS58112372A (en) | Manufacture of semiconductor device |