JPS6042892A - Printed circuit board - Google Patents
Printed circuit boardInfo
- Publication number
- JPS6042892A JPS6042892A JP58150619A JP15061983A JPS6042892A JP S6042892 A JPS6042892 A JP S6042892A JP 58150619 A JP58150619 A JP 58150619A JP 15061983 A JP15061983 A JP 15061983A JP S6042892 A JPS6042892 A JP S6042892A
- Authority
- JP
- Japan
- Prior art keywords
- board
- printed circuit
- circuit board
- product name
- information
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、エポキシ、セラミック等の絶縁基材の表面に
、信号接続、あるいは部品取付用の導体パターンを形成
する印刷回路基板に係り、特にノ(ターンの導通テスト
時の基板品名、あるいは、眉毛、層履歴等の基板情報の
畔取りに好適な印刷回路基板に関するものである。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a printed circuit board in which a conductive pattern for signal connection or component mounting is formed on the surface of an insulating base material such as epoxy or ceramic, and particularly relates to a (This relates to a printed circuit board suitable for removing board information such as board product name, eyebrows, layer history, etc. during a turn continuity test.
[発明の背景]
従来の印刷回路基板の構造の1例を第1図に示す、同図
(a)は基板の全体平面図、同図(b)は基板の一部断
面図を示してい・る、@ 1はエポキシ、あるいはセラ
ミック等の絶縁基材4の表面に信号ラインまたはパッド
の導体パターン5を印刷、あるいゆエツチング技術によ
り形成した印刷回路基板である。これらの導体パターン
5は、印刷回路基板1の中央部の配線領域2の中に配置
されている。一方、これらの導体パターン5の識別のた
めに各基板には、基板品名1層名および層履歴等の基板
情報を表示するが、これらの表示は前記配線領域2の外
側の基板情報表示領域3にアルファベットまたは数字を
用いて行うの゛が一般的である。[Background of the Invention] An example of the structure of a conventional printed circuit board is shown in FIG. 1. FIG. 1(a) shows an overall plan view of the board, and FIG. 1 is a printed circuit board in which a conductive pattern 5 of a signal line or pad is formed on the surface of an insulating base material 4 made of epoxy or ceramic by printing or etching technology. These conductor patterns 5 are arranged in the wiring area 2 at the center of the printed circuit board 1 . On the other hand, in order to identify these conductor patterns 5, board information such as the board product name, first layer name, and layer history is displayed on each board, but these displays are performed in the board information display area 3 outside the wiring area 2. It is common to use alphabets or numbers.
上記基板情報の表示例の詳細を第2図に示す。FIG. 2 shows details of a display example of the board information.
この図の例では、A、100が基板品名、次のAが基板
の眉毛、最後の0がパターンの履歴を示している。これ
らの基板情報の表示領域3は、配線領域2の外側に設け
られている。In the example of this figure, A, 100 indicates the board product name, the next A indicates the eyebrows of the board, and the last 0 indicates the pattern history. The display area 3 for these board information is provided outside the wiring area 2.
げ、般の印刷回路基板1は、前記の基材1が1枚のもの
から10枚以上積層した多層基板のものがある。これら
の基板のテストは、導体パターン5の断線と、導体パタ
ーン5間の短絡を調べるものが主である。この検査方法
は、基板の各格子(バット)、上に導通検査用のプロニ
ブピンを立て、このプローブピン間の断線、短絡情報を
、被テスト基板の品名に対応した導通検査データと照合
してテストを行うというものである。この゛場合、従来
は基板のテスト時に、被テスト基板の品名1、眉毛。However, general printed circuit boards 1 range from one base material 1 to multilayer boards having ten or more base materials laminated. The tests for these boards mainly involve checking for disconnections in the conductor patterns 5 and short circuits between the conductor patterns 5. This testing method involves setting up probe pins for continuity testing on each grid (butt) of the board, and comparing the disconnection and short circuit information between these probe pins with the continuity testing data corresponding to the product name of the board under test. The idea is to do this. In this case, conventionally, when testing a board, the product name 1 of the board to be tested, the eyebrows.
層履歴等の基板情報を基板の表示領域3を見ながら人手
によって導通検査装置に入力し、該基板情報に対応する
被テスト基板のテストデータをファイル等から読出して
おり、製造ラインの作業効率向上のネックになっていた
。また、この対策としてアルファベット、数字等で書い
た品名1層名。Board information such as layer history is manually input into the continuity testing device while looking at the display area 3 of the board, and the test data of the tested board corresponding to the board information is read out from a file, etc., improving the work efficiency of the production line. It was becoming a bottleneck. In addition, as a countermeasure for this, the product name is written in alphabets, numbers, etc. in the first layer.
層履歴等の基板情報を光学系の文字読取り機により自動
曲に判読して入力する方法もあるが、この文字読取り機
が余計に必要となるため、高価な導通検査装置となると
いう欠点もあっ、た。There is also a method of automatically reading and inputting board information such as layer history using an optical character reader, but this requires an additional character reader and has the disadvantage of requiring an expensive continuity testing device. ,Ta.
本発明は、上述の点にかんがみてなされたもので、印刷
回路基板の導通検査時、特別な9判別機を用いることな
く、基板の品名等を自動的に判別し、被テスト基板の導
通テストデータをセットして基板のテストを効率的に行
うことができるよ1にした印刷回路基板を提供すること
を目的とする。The present invention has been made in view of the above-mentioned points, and is capable of automatically determining the product name of the board, etc., without using a special 9-discriminator when testing the continuity of a printed circuit board, and testing the continuity of the board under test. An object of the present invention is to provide a printed circuit board on which data can be set and the board can be tested efficiently.
〔発明あ概要]
本発明の要点は、印刷回路基板の表面に基板の品名1層
名、層履歴等の基板情報を通常信号等の導体パターンと
同様のパターンで形成し、基板テストに際して導通検査
装置で前記基板情報を検出できるようにしたことである
。[Summary of the invention] The main point of the present invention is to form board information such as the board product name, layer name, layer history, etc. on the surface of a printed circuit board in a pattern similar to a conductor pattern for normal signals, etc., and conduct continuity inspection during board testing. The device is capable of detecting the board information.
以下本発明の実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below based on the drawings.
第3図は本発明に係る印刷回路基板の一部を示す図であ
り、基板1の配線領域2の外側にある基板情報の表示領
域3には、基板の品名を表わす5個のバット6(第2図
のA100−に対応する)、基板の眉毛を表示する2個
のバット7(第2図、の、−A −L;対応する)、基
板の層履歴を表示する同じく2個のバット8°(第2図
の一部に対応する)が設けられている。さらに1個の基
準パット9が設けられ、この基準パッド9と前記基板の
品名、眉毛、層履歴表示用パッド6〜8を接続するライ
ンlOが設けられている。基板1における導体パターン
5の形成方法および配線領域2内のパターンについては
、従来構成と同一であり、基板の品名、眉毛、層履歴を
表示するバット6〜8.基準バット9、およびラインl
Oを、配線領域2内の導体パターン5と同様の方法で形
成する。FIG. 3 is a diagram showing a part of the printed circuit board according to the present invention. In the board information display area 3 outside the wiring area 2 of the board 1, there are five bats 6 ( (corresponding to A100- in Figure 2), two bats 7 that display the eyebrows of the board (corresponding to -A-L; in Figure 2), and two bats that display the layer history of the board. 8° (corresponding to part of FIG. 2). Furthermore, one reference pad 9 is provided, and a line 1O is provided that connects this reference pad 9 to the pads 6 to 8 for displaying the product name, eyebrows, and layer history of the substrate. The method of forming the conductor pattern 5 on the board 1 and the pattern in the wiring area 2 are the same as the conventional structure, and bats 6 to 8 displaying the product name, eyebrows, and layer history of the board. Reference bat 9 and line l
O is formed in the same manner as the conductor pattern 5 in the wiring region 2.
いま、基準パット9と接続されているパッドを1′11
″、離れている場合を0”とすれば、第3図の場合、品
名は”10100”1層名はtt 10 N、層履歴は
”01’″と、2進化情報で表示される。言うまでもな
く、品名、眉毛等が変わればライン10のパターンも変
わり、2進化情報は異ってくる。Now, the pad connected to the reference pad 9 is 1'11
'', and if the distance is 0, then in the case of FIG. 3, the product name is ``10100'', the first layer name is tt 10 N, and the layer history is ``01'', which are displayed as binary information. Needless to say, if the product name, eyebrows, etc. change, the pattern of line 10 will also change, and the binary information will differ.
、上記の印刷回路基板の導通テストは、第4図に示すよ
うな、導通検査装置の導通検査プローブ21に設けられ
た多数のピン22を配線領域2内の導体パターン5およ
びバット6〜9に立て;このピン22の出力を処理装置
23で走査して行う、この際、基準パット9と基板の品
名1層名、層履歴を表示するパット6〜8間の導通チェ
ックにより、導体パターンと共に品名、眉毛、層履歴の
2進化情報”101001001”も読み取られる。処
理装置23は、読み取った基板情報により該基板1に対
応する導通検査データをファイル26から読み出し、こ
れと導通検査ブロー、ブ21より入力される配線領域2
内の導体パターンと比較してテストを行う、このテスト
結果を処理装置23はプリンタ24に出力し、プリンタ
用紙25に導通検査結果を記録する。この時、処理装置
23は基板情報もプリンタ24に出力すると。The continuity test for the printed circuit board described above is performed by connecting a large number of pins 22 provided on the continuity test probe 21 of the continuity test device to the conductor pattern 5 and bats 6 to 9 in the wiring area 2, as shown in FIG. The output of this pin 22 is scanned by the processing device 23. At this time, by checking the continuity between the reference pad 9 and the pads 6 to 8 that display the product name, layer name, and layer history of the board, the product name is displayed along with the conductor pattern. , eyebrows, and layer history binary information "101001001" are also read. The processing device 23 reads the continuity test data corresponding to the board 1 from the file 26 based on the read board information, and uses this and the continuity test data input from the wiring area 2 input from the continuity test blow 21.
The processing device 23 outputs the test results to the printer 24 and records the continuity test results on printer paper 25. At this time, the processing device 23 also outputs board information to the printer 24.
とにより、用紙25上には検査結果と共に基板情報も図
のように記録される。As a result, board information is recorded on the paper 25 along with the inspection results as shown in the figure.
第5図は本発明に係る他の印刷回路基板の基板情報を表
示する部分を示す図で、基準パターン(第3図のバット
9およびラインlOに対応する)を基板1の裏面に設け
、裏面との接続用スルーホール穴11の有無によって2
進化データを作る。いま、スルーホール11があり、裏
面との接続がある場合を11″′、スルーホール穴11
がなく、接続のない場泰を# O#lとすると、第5図
の場合、品名を表示するバット6は’11010”、眉
毛を表示するパット7は’ot”、層履歴を表示するパ
ット8は’ot”となる。FIG. 5 is a diagram showing a part of another printed circuit board according to the present invention for displaying board information, in which a reference pattern (corresponding to the batt 9 and line IO in FIG. 3) is provided on the back side of the board 1, and the back side 2 depending on the presence or absence of through-hole hole 11 for connection with
Create evolutionary data. Now, there is a through hole 11, and if there is a connection with the back side, it is 11'', through hole hole 11
If there is no connection and there is no connection, #O#l, in the case of Figure 5, the bat 6 that displays the product name is '11010', the pad 7 that displays the eyebrows is 'ot', and the pad that displays the layer history is '11010'. 8 becomes 'ot'.
第6図は、第5図と同様、本発明に係る他の印刷回路基
板の基板情報を表示する部分を示す図で、2個の基準パ
ット9a、9bを設け1品名1層名。FIG. 6, similar to FIG. 5, is a diagram showing a part for displaying board information of another printed circuit board according to the present invention, in which two reference pads 9a and 9b are provided to display one product name and one layer name.
層履歴粉表示するバット6〜8の内、基準バット9aと
ライン10aで接続されているものは#1lllQ基準
パット9bとライン10bで接続されているものはII
2 II、基準パット9a、9bのいずれとも接続さ
れていないものは110 uを示すものとすると、同図
の場合、品名を表示するパット6は’0211G”、眉
毛を表示するパット7は“12″、層履歴を表示するバ
ット8はII 20 IIとなる。また、第6図の場合
は基準パット9a、9b−(7)2個とし、3進の場合
を示したが、基準パット3個、4個と増すことにより、
4進、5進にもすることができ、基板情報のデータを作
るのにビット数を減すことができる。Among the bats 6 to 8 to display the layer history powder, those connected to the reference bat 9a and line 10a are #1lllQ those connected to the reference pad 9b and line 10b are II
2 II, if it is not connected to either of the reference pads 9a or 9b, it indicates 110u. In the case of the same figure, the pad 6 that displays the product name is '0211G', and the pad 7 that displays the eyebrows is '12 '', the bat 8 that displays the layer history is II 20 II.Also, in the case of Fig. 6, there are two standard pads 9a, 9b-(7), and a ternary case is shown, but three standard pads are used. , by increasing the number to 4,
It can also be converted into quaternary or quinary notation, and the number of bits can be reduced to create board information data.
なお、上記品名等の基板情報の表示方法は、一枚の基材
、あるいは多数枚積層数の基板にも適用できることはい
うまでもない。また、基準パットの設置の代り5別な共
通パターンを使用し、バット6〜8とその共通パターン
との導通をチェックするようにしても基板情報は表示で
きる。It goes without saying that the above method for displaying board information such as product name can be applied to a single base material or a board with a large number of laminated boards. Further, the board information can be displayed by using five different common patterns instead of setting the reference pads and checking the continuity between the bats 6 to 8 and the common patterns.
以上説明したように、本発明に係る印刷回路基板は、基
板の導通テスト時、基板の品名等の基板情報のデータを
人手によって外部より入力する必要がなく、通常の導通
検査装置の導通検査の過程で自動的に判読し、導通検査
データをファイルより取出し、導通検査を行うことがで
きるので、導通検査作業の効率が向上すると共に、基板
情報データの誤入力が防止できる。また、高精密の光学
文字読取り装置が必要ないので導通検査が安価にできる
と共に、さらに、通常の導体パターンと同じ方法で基板
情報が表示できるので、従来の英数字表現に比べ高密度
化が可能になる等の優れた効果を有する。As explained above, the printed circuit board according to the present invention eliminates the need to manually input board information data such as the product name of the board from the outside during the continuity test of the board, and the printed circuit board according to the present invention eliminates the need for manually inputting board information data such as the product name of the board from the outside. Since the continuity test data can be automatically read during the process, the continuity test data can be extracted from the file, and the continuity test can be performed, the efficiency of the continuity test work can be improved and erroneous input of board information data can be prevented. In addition, since there is no need for a high-precision optical character reader, continuity testing can be done at low cost.Furthermore, since board information can be displayed in the same way as a normal conductor pattern, it is possible to achieve higher density than conventional alphanumeric representation. It has excellent effects such as:
第1図は従来の印刷回路基板構造の1例を示す図で、同
図(a’)は基板の全体平面図、同図(b)は基板の一
部断面図、第2図は従来の印刷回路基板の基板情報の表
示例を示す図、第3図は本発明に係る印刷回路基板の基
板情報の表示例を示す図、第4図は導通検査装置のブロ
ック図、第5図、第6図は本発明に係る印刷回路、基板
の他の基板情報の表示例を示す図である。
1・・・印刷回路基板、2・・・配線領域、3・・・基
板情報表示領域、4・・・絶縁基材、5・・・導体パタ
ーン、6・・・品名表示用パッド、7・・・眉毛表示用
パッド、8・・・層履歴表示用パッド、9・・・基準パ
ッド。
10・・・ライン、11・・・スルーホール穴、21・
・・導通検査プローブ、22・・・ピン、23・・・処
理装置、24・・・プリンタ、25・・・プリンタ用紙
、26・・・ファイル。
第1図
第2図
第3図
第4図
第5図
第6図Figure 1 is a diagram showing an example of a conventional printed circuit board structure. Figure (a') is an overall plan view of the board, Figure (b) is a partial cross-sectional view of the board, and Figure 2 is a diagram showing an example of a conventional printed circuit board structure. 3 is a diagram showing an example of displaying board information on a printed circuit board according to the present invention; FIG. 4 is a block diagram of a continuity testing device; FIGS. FIG. 6 is a diagram showing an example of displaying other board information of the printed circuit and board according to the present invention. DESCRIPTION OF SYMBOLS 1... Printed circuit board, 2... Wiring area, 3... Board information display area, 4... Insulating base material, 5... Conductor pattern, 6... Product name display pad, 7... ...Eyebrow display pad, 8...Layer history display pad, 9...Reference pad. 10...Line, 11...Through hole, 21.
... Continuity test probe, 22... Pin, 23... Processing device, 24... Printer, 25... Printer paper, 26... File. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6
Claims (1)
用の導体パターンを形成し、この基材を単体あるいは複
数枚積層した印刷回路基板において、前記基板上に基板
情報を示すパターンを前記導体パターンと同様の形式で
形成したことを特徴とする印刷回路基板。(1) In a printed circuit board in which a conductor pattern for attaching components or signal connection is formed on the surface of an insulating base material, and this base material is used singly or in a stack, a pattern indicating board information is placed on the board. A printed circuit board characterized in that it is formed in the same format as a pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58150619A JPS6042892A (en) | 1983-08-18 | 1983-08-18 | Printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58150619A JPS6042892A (en) | 1983-08-18 | 1983-08-18 | Printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6042892A true JPS6042892A (en) | 1985-03-07 |
Family
ID=15500823
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58150619A Pending JPS6042892A (en) | 1983-08-18 | 1983-08-18 | Printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6042892A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06288030A (en) * | 1993-04-02 | 1994-10-11 | Natl House Ind Co Ltd | Eaves |
| JP2007234944A (en) * | 2006-03-02 | 2007-09-13 | Fujitsu Ltd | Silk printing plate number discrimination method and printed circuit board |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5015068A (en) * | 1973-06-15 | 1975-02-17 | ||
| JPS5635492A (en) * | 1979-08-29 | 1981-04-08 | Nippon Electric Co | Electronic circuit board |
| JPS56122185A (en) * | 1980-03-03 | 1981-09-25 | Tokyo Print Kogyo Co Ltd | Method of indicating lot number or like in printed circuit board |
-
1983
- 1983-08-18 JP JP58150619A patent/JPS6042892A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5015068A (en) * | 1973-06-15 | 1975-02-17 | ||
| JPS5635492A (en) * | 1979-08-29 | 1981-04-08 | Nippon Electric Co | Electronic circuit board |
| JPS56122185A (en) * | 1980-03-03 | 1981-09-25 | Tokyo Print Kogyo Co Ltd | Method of indicating lot number or like in printed circuit board |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06288030A (en) * | 1993-04-02 | 1994-10-11 | Natl House Ind Co Ltd | Eaves |
| JP2007234944A (en) * | 2006-03-02 | 2007-09-13 | Fujitsu Ltd | Silk printing plate number discrimination method and printed circuit board |
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