JPS6043080A - Inverter circuit - Google Patents
Inverter circuitInfo
- Publication number
- JPS6043080A JPS6043080A JP58151445A JP15144583A JPS6043080A JP S6043080 A JPS6043080 A JP S6043080A JP 58151445 A JP58151445 A JP 58151445A JP 15144583 A JP15144583 A JP 15144583A JP S6043080 A JPS6043080 A JP S6043080A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- resistor
- source
- voltage
- diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 claims description 5
- 238000004804 winding Methods 0.000 abstract description 14
- 238000010586 diagram Methods 0.000 description 12
- 238000009499 grossing Methods 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 3
- 229920006395 saturated elastomer Polymers 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
- H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
- H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
- H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5383—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a self-oscillating arrangement
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、開閉素子として用いた電界効果トランジスタ
（以下Ｍ ＯＳ Ｆ ＥＴという）のターンオフ時のス
イツナング特性を改良したインノ（−夕回路に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inno-electronic circuit that improves the switch-off characteristic of a field effect transistor (hereinafter referred to as MOS FET) used as a switching element at the time of turn-off.
Ｍ ＯＳ Ｆ ＥＴは高速度のターンオン、オフが可能
であるが、このドレーン、ソース間のターンオン、オフ
はゲート、ソース間の電圧の立上り、立下り速度に左右
される。実際には、ゲート、ソース間に比較的大きなキ
ャパシタンスが存在するので、この充電の速度がそのま
まＭＯ，５ＦＥＴのターンオン、オフの速度を規制する
。また、一般に第１図に示すように制御電圧印加回路（
１１とＭＯ８’Ｆ ］（Ｔ （２１のゲート間には通常
抵抗（３）を挿入する。The MOSFET can be turned on and off at high speed, but the turn on and off between the drain and the source depends on the rise and fall speed of the voltage between the gate and the source. Actually, since a relatively large capacitance exists between the gate and the source, the charging speed directly controls the turn-on and turn-off speed of the MO, 5FET. In addition, generally, as shown in Fig. 1, a control voltage application circuit (
11 and MO8'F ](T (A resistor (3) is usually inserted between the gates of 21.
これはＭ Ｏ８１ｉ’ Ｅ Ｔ （２）のゲート、ソー
ス間のキャパシタンスと制御電圧印加回路（１）との間
の寄生振動を防止するためであるが、これは第１図のよ
うにトランジスタ（４） （５）を挿入して折角Ｍ Ｏ
Ｓ Ｆ Ｅ Ｔ （２１のゲート、ソース間への電圧の
印加を早くしようとしても、この抵抗（３）によってゲ
ート、ソース間電圧（’Ｖｇｓ ）の変化速度は制限さ
れる。なお、第１図において、（６）は主変圧器、（７
）は２次側の整流平滑回路である。This is to prevent parasitic vibration between the capacitance between the gate and source of M O81i'ET (2) and the control voltage application circuit (1), but this is because the transistor (4 ) (5) is inserted and M O
S F E T (Even if we try to speed up the application of voltage between the gate and source of 21, the rate of change of the voltage ('Vgs) between the gate and source is limited by this resistor (3). Note that Fig. 1 In, (6) is the main transformer, (7
) is a rectifying and smoothing circuit on the secondary side.
本発明は、以上のような従来の問題点を解決するために
なされたもので、電圧印加回路に挿入した抵抗と並列に
ダイオードを挿入してなるものである。その結果１．Ｍ
Ｏ８ＦＥ’ｌ”のターンオフ時の速度を可及的に高める
ことができる。The present invention has been made to solve the above-mentioned conventional problems, and is made by inserting a diode in parallel with a resistor inserted in a voltage application circuit. The result 1. M
The turn-off speed of O8FE'l'' can be increased as much as possible.
以下、本発明によるＭＯＳ Ｂ’Ｆ Ｔ、を用いたイン
バータ回路の実施例を第２図以下の図面に基づいて説明
する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an inverter circuit using a MOS B'FT according to the present invention will be described below with reference to FIG. 2 and the following drawings.
第２図は本発明の基本的回路図を示し、また第３図は具
体的回路図を示すものである。これらの図において、（
＋、ｌ （−）は正負の入力電源端子で、一方の電源端
子（＋）から主変圧器（６）の１次巻線（８）、ＭＯＳ
ＦＥＴ（２＋のドレイン、ソースを経て他方の電源端子
（−）に結合されている。また、前記Ｍ、０８ Ｆ Ｅ
Ｔ（２）のゲート、ソース間には、制御電圧印加回路（
１）が結合されている。この制御電圧印加回路（１）は
、前記主変圧器（６）に設けられた補助巻線（９）の両
端（二抵抗Ｑ０を介して飽和変圧器ａυの１次巻線ｏｚ
の両端に結合し、また、飽和変圧器（１１１の２次巻線
α３）の一端は抵抗（３）を”介してＭ ＯＳ Ｆ ’
Ｂ Ｔ （２＋のゲート：二結合し、他端はＭＯＳＦＥ
Ｔ（２＋のソース１二結合されている。そして、本発明
では、特よ＝、前記抵抗（３）と並列に、ＭＯＳ Ｆ
Ｅ Ｔ’（２１のゲート方向にアノードが向くようにダ
イオード（１４１が挿入されている。FIG. 2 shows a basic circuit diagram of the present invention, and FIG. 3 shows a specific circuit diagram. In these figures, (
+, l (-) are positive and negative input power supply terminals, and from one power supply terminal (+) to the primary winding (8) of the main transformer (6), MOS
FET (connected to the other power supply terminal (-) via the drain and source of 2+. Also, the above M, 08 F E
A control voltage application circuit (
1) are combined. This control voltage application circuit (1) connects both ends of the auxiliary winding (9) provided in the main transformer (6) (through two resistors Q0 to the primary winding oz of the saturation transformer aυ).
, and one end of the saturation transformer (secondary winding α3 of 111) is connected to the MOS F' through the resistor (3).
B T (2+ gate: 2 coupled, other end is MOSFE
The source 1 of T(2+) is coupled with the MOS F
A diode (141) is inserted so that its anode faces toward the gate of E T' (21).
３図の回路において、前記飽和変圧器（１１）の２次巻
線Ｑ３）ト・ＭＯｓ Ｆ Ｅ Ｔ（２）ｃＤソース間ニ
！イオ−）’Ｑ５１゛を挿入し、同のダイオード（ＩＱ
のカソード側と前記正側端子（＋）との間に、抵抗αＧ
）と、補助巻線（Ｉｎで開閉される電子的開閉素子（１
８）からなり起動後に起動側の影響を消滅させる手段（
１９）を結合する。また、前記タイオード０！５１と並
列に、コンデンサ（２０’を結合するとともに、補助巻
線（２１）で開閉される電子的開閉素子（２２からなり
起動後のダイオード（１５１の電圧を消滅させる手段（
２）を結合する。これらの手段（１９） （２３１は両
方設けてもよ−いし、少なくともいずれか一方でありで
もよい。前記変圧器（６）の２次巻線例には、整流平滑
回路（７）、誤差増幅回路（２５）を介して出力端子０
６）（２７）が結合されている。In the circuit shown in Fig. 3, the secondary winding of the saturation transformer (11) is connected between the secondary winding Q3) and the MOs FET(2)cD source. Insert the same diode (IQ51) and
A resistor αG is connected between the cathode side and the positive side terminal (+).
) and an electronic switching element (1
8) means to eliminate the influence of the activation side after activation (
19). Further, in parallel with the diode 0!51, a capacitor (20') is coupled, and a means for extinguishing the voltage of the diode (151) consisting of an electronic switching element (22) that is opened and closed by an auxiliary winding (21). (
2) Combine. Both of these means (19) (231) may be provided, or at least one of them may be provided. Examples of the secondary winding of the transformer (6) include a rectifier and smoothing circuit (7), an error amplification circuit, and an error amplification circuit. Output terminal 0 via circuit (25)
6) (27) is combined.
つぎに第３図の回路の作用を第５図および第６図の波形
図ににり説明する。第５図は正常運転時の波形図であり
、第６図はその′ターン、オフ時の時間軸を拡大した波
形図である。まず、飽和変圧器αυにより自励発振動作
の概略を説明すると、第３図の主変圧器（６）の補助巻
線（９）より電圧（Ｖ、）が取り出されて、飽和時の電
流制限抵抗ＱＯＩを介して飽和変圧器αυに供給される
。飽和変圧器ａυの２次巻線＜１３１は図示のような方
向に抵抗（３）を介してＭＯ８Ｆ ＥＴ （２＋のゲー
ト、ソース間に結ばれているので、第５図のＴ１、Ｔ２
間においては前記電圧（ｖ９）が飽和変圧器（１１）を
介して電圧（Ｖｇｓ）が印加され、ＭＯ８１ｉ’ Ｅ
Ｔ （２＋の導通が保持されている。なお、導通中、ゲ
ート電流（Ｉｇ）はほとんど流れていないので、■。Next, the operation of the circuit shown in FIG. 3 will be explained with reference to the waveform diagrams shown in FIGS. 5 and 6. FIG. 5 is a waveform diagram during normal operation, and FIG. 6 is an enlarged waveform diagram showing the time axis during turn and off. First, to explain the outline of the self-oscillation operation using the saturation transformer αυ, the voltage (V, ) is taken out from the auxiliary winding (9) of the main transformer (6) in Figure 3, and the current is limited at saturation. It is supplied to the saturation transformer αυ via the resistor QOI. The secondary winding <131 of the saturation transformer aυ is connected between the gate and source of MO8FET (2+) through the resistor (3) in the direction shown, so T1 and T2 in Figure 5
In between, the voltage (Vgs) is applied to the voltage (v9) through the saturation transformer (11), and the voltage (Vgs) is applied to the MO81i' E
T (2+ conduction is maintained. Note that during conduction, almost no gate current (Ig) flows, so ■.
：、Ｖｇｓとして説明しても差支えない。:, Vgs.
１２時に近くなって飽和変圧器Ｑｌ）が一定電圧時間積
を受けるとこの飽和変圧器（１１）は飽和する。飽和す
ると飽和変圧器ａυは短絡されたと同様になるのでゲー
ト、ソース間電圧（ｖｇｓ）は失って１２時において遮
断される。この時、補助巻線（９）からの電流「ま抵抗
α０）によって制限される。Close to 12 o'clock, when the saturation transformer Ql) is subjected to a constant voltage-time product, this saturation transformer (11) becomes saturated. When saturated, the saturation transformer aυ becomes as if it were short-circuited, so the voltage between the gate and the source (vgs) is lost and it is cut off at 12 o'clock. At this time, the current from the auxiliary winding (9) is limited by the resistance α0.
’ｒ２−Ｔ３間にＭ ＯＳ Ｆ Ｅ Ｔ （２ｉは遮断
されたままであるが、主変圧器（６）がＭ ＯＳ Ｆ
Ｅ Ｔ （２１の導通時（Ｉｌ１１Ｔ２時）に受けとっ
たときと等量の一定時間積を受けて１３時に至ると反転
を開始し、ゲート、ソース間電圧（Ｖｇｓ）は正電圧と
なり、これがＭＯ８Ｆ Ｅ Ｔ （２１のゲートしきい
電圧を越え、ターンオンし、導通を開始し、以下同様に
して発振動作を繰返す。'r2-T3 (2i remains cut off, but the main transformer (6)
E T (When MO8F E T(21) is exceeded, the gate is turned on, conduction begins, and the oscillation operation is repeated in the same manner.
つぎに、本発明のダイオード（１４１のない場合のター
ン、オフ時の各部の動作を第６図によって説明する。Next, the operation of each part of the present invention when the diode (141 is not provided) during turn-on and off-state will be explained with reference to FIG.
まず、飽和変圧器（１１）が１１時に飽和して短絡状態
になると飽和変圧器（１１１は急速にその電圧（ｖｌｌ
）が消滅する。しかし、抵抗（３）に妨げられてゲート
、ソース間に蓄えられていた電荷は有限の電流（Ｉｇ）
となって流れ、これによってゲート、ソース間電圧（７
ｇｓ ）は図示のように比較的ゆっくりした速度で下降
を始める。１２時に至り、ゲート、ソース間電圧（Ｖｇ
ｓ）がゲートしきい電圧以下になるとドレイン、ソース
間は電圧（Ｖｄｓ）を負担し始める。つまりターンオフ
開始する。以下、このゲート、ソース間電圧ｆｆｇｓ）
の低下に追従してドレイン、ソース間電圧（Ｖｄｓ）は
増加しｔ３に至り、ターンオフは完了する。First, when the saturation transformer (11) becomes saturated at 11 o'clock and becomes short-circuited, the saturation transformer (111) rapidly increases its voltage (vll
) disappears. However, the charge stored between the gate and source is blocked by the resistor (3) and becomes a finite current (Ig).
This causes the voltage between the gate and source (7
gs ) begins to descend at a relatively slow speed as shown. At 12 o'clock, the voltage between the gate and source (Vg
When s) becomes less than the gate threshold voltage, a voltage (Vds) begins to be applied between the drain and source. In other words, turn-off begins. Hereinafter, this gate-source voltage ffgs)
Following the decrease in voltage, the drain-source voltage (Vds) increases and reaches t3, at which time the turn-off is completed.
以上の説明のように、ドレイン、ソース間電圧（Ｖｄｓ
）の増加の速度、つまりターンオフ速度はゲート、ソー
ス間電圧（ｖｇｓ）の変化の速度に比例する。このため
、抵抗（３）を小さくすることが望ましいが、これはゲ
ート、ソース間のキャパシタンスとの間の振動を阻止す
るために一定量以上が必要である。この時本発明のダイ
オード（１４１を抵抗（３）の両端に結合すると、振動
は抵抗（３）によって阻止し、かつゲート、ソース間電
圧（Ｖｇｓ）の変化の速度を極限まで高めることが可能
である。As explained above, the drain-source voltage (Vds
), that is, the turn-off speed is proportional to the speed of change in the gate-source voltage (vgs). For this reason, it is desirable to reduce the resistance (3), but it needs to be at least a certain amount in order to prevent vibration between the gate and the source capacitance. At this time, by connecting the diode (141) of the present invention to both ends of the resistor (3), the vibration can be blocked by the resistor (3) and the speed of change of the gate-source voltage (Vgs) can be increased to the maximum. be.
以上の状況をさらに第７図によって説明する。The above situation will be further explained with reference to FIG.
まず、１８時での飽和変圧器側の飽和および電圧（ｖｌ
ｌ）の降下は第６図の従来例と同様であるが、ゲート、
ソース間の電荷はダイオード（１４１を通じて急速に放
電され、ｔｌ、ｔ２．１３間のゲート電流のような急峻
な放電電流が流れ、これによりゲート、ソース間電圧（
Ｖｇｓ）は急速に低下し、これによりドレイン、ソース
間電圧（Ｖｄｓ）は急速に電圧を負担し始め、従来方式
よりも著しくそのスイッチング特性を改善するものであ
る。ちなみに第７図の１□〜１３間の電流（Ｉｄｃ）は
ドレイン、ソース間のキャパシタンスの充電時のもので
あり、これはターンオン時に電源に返還されるので、電
力損失は形成せず、全体に能率も甚しく改善される。な
お、本発明はターンオン時の改善には作用しないが第３
図、第４図のように出力側で電力、電圧の制御が行なわ
れるコンバータにおい−Ｃは、ターンオン時のドレイン
電流は零であるのでもともとターンオン時の電力損失は
ほとんど零であることと相俟って、ターンオフ時のみの
改善で回路全体としては充分である。このことは第１図
のフライバック方式においてもターンオン電流はほとん
ど零で力】るので、上述の場合と同様である。First, the saturation and voltage on the saturation transformer side at 18:00 (vl
The descent of l) is similar to the conventional example shown in Fig. 6, but the gate,
The charge between the source is rapidly discharged through the diode (141), and a steep discharge current such as the gate current between tl and t2.13 flows, which causes the voltage between the gate and the source (
The drain-source voltage (Vds) rapidly decreases, and the drain-source voltage (Vds) quickly begins to bear the voltage, which significantly improves the switching characteristics over the conventional system. By the way, the current (Idc) between 1□ and 13 in Figure 7 is when the capacitance between the drain and source is charged, and this is returned to the power supply at turn-on, so no power loss occurs and the overall Efficiency is also greatly improved. Note that the present invention does not improve the turn-on time, but the third
In a converter where the power and voltage are controlled on the output side as shown in Figure 4, the drain current at turn-on is zero, so the power loss at turn-on is essentially zero. Therefore, improvement only at turn-off is sufficient for the entire circuit. This is the same as in the above case since the turn-on current is almost zero even in the flyback method shown in FIG.
本発明は、第４図に示すような２−個のＭＯＳ ＦＷ
Ｔ （２ａ） （２ｂ）をプッシュプル結合した場合も
そのまま利用でき、その作用も前述と略同・様である。The present invention utilizes two MOS FWs as shown in FIG.
Push-pull coupling of T (2a) and (2b) can also be used as is, and the effect is almost the same as described above.
本発明は上述のようにＭ Ｏ５’Ｆ ｐ Ｔのターンオ
フ時のスイッチング特性を著しく改善したものであるが
、本発明の方式は出力側を磁気増巾器によって電圧制御
し、入力インバータ部分を飽和変圧器とＭＯＳＦＥＴに
より自励発振動作せしめた全体構成の回路に最も幼葉的
に作用し、その発振周波数をＭＯＳＦＥＴの特性の限界
まで利用してｉｏｏ。As mentioned above, the present invention significantly improves the switching characteristics at turn-off of M O5'F p T, but the method of the present invention controls the voltage on the output side using a magnetic amplifier and saturates the input inverter section. It acts in the most childish manner on the overall circuit that generates self-excited oscillation using a transformer and MOSFET, and utilizes the oscillation frequency to the limit of the MOSFET's characteristics.
〜１５００ＫＩ（ｚの超高周波コンバータを、能率の低
下をみることなく達成させることが可能である。It is possible to achieve very high frequency converters of ~1500 KI (z) without any loss in efficiency.
第１図はＭ ＯＳ Ｆ Ｅ Ｔを用いた従来のインバー
タ回路図、第２図は本発明のインバータ回路の基本的電
気回路図、第３図は本発明のインバータ回路の具体的電
気回路図、＄４図は本発明の他の実施例の電気回路図、
第５図は従来方式における正常運転時の出力波形図、第
６図は第５図におけるターンオフ時の時間軸を拡大した
波形図、第７図は本発明における回路の波形図である。
（１１・・・制御電圧印加回路、（２１（２ａ）（２ｂ
） ・＋＋ Ｍ ＯＳ ＦＥＴ 、 （３に３ａ）（３
ｂ）−抵抗、（（３）−、主変圧器、（７） ・・・整
流平滑回路、（９）・・・補助巻線、（１０）・・・抵
抗、（ｌｌ）・・・飽和変圧器、α４１（１４ａ）（１
４ｂ）−ダイオード。FIG. 1 is a conventional inverter circuit diagram using MOSFET, FIG. 2 is a basic electric circuit diagram of the inverter circuit of the present invention, and FIG. 3 is a specific electric circuit diagram of the inverter circuit of the present invention. Figure 4 is an electrical circuit diagram of another embodiment of the present invention;
FIG. 5 is an output waveform diagram during normal operation in the conventional system, FIG. 6 is an enlarged waveform diagram of the time axis at turn-off in FIG. 5, and FIG. 7 is a waveform diagram of the circuit according to the present invention. (11... control voltage application circuit, (21 (2a) (2b
) ・++ M OS FET, (3 to 3a) (3
b) - Resistance, ((3) -, Main transformer, (7)... Rectifier and smoothing circuit, (9)... Auxiliary winding, (10)... Resistance, (ll)... Saturation Transformer, α41 (14a) (1
4b) - diode.
Claims (1)
圧器を主体として構成され、前記電界効果トランジスタ
を適当な方法にて発振させるインバータ回路において、
前記電界効果トランジスタのゲート、ソース間に挿入さ
れた制御電圧印加回路に、抵抗を挿入するとともに、こ
の抵抗と並列に、前記電界効果トランジスタのゲート方
向にアノードが向くようにしてダイオードを挿入してな
ることを特徴とするインバータ回路。(1) In an inverter circuit mainly composed of a switching element made of a field effect transistor and a main transformer, the inverter circuit causes the field effect transistor to oscillate in an appropriate manner,
A resistor is inserted into a control voltage application circuit inserted between the gate and source of the field effect transistor, and a diode is inserted in parallel with the resistor with an anode facing toward the gate of the field effect transistor. An inverter circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58151445A JPS6043080A (en) | 1983-08-19 | 1983-08-19 | Inverter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58151445A JPS6043080A (en) | 1983-08-19 | 1983-08-19 | Inverter circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6043080A true JPS6043080A (en) | 1985-03-07 |
| JPH0572192B2 JPH0572192B2 (en) | 1993-10-08 |
Family
ID=15518752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58151445A Granted JPS6043080A (en) | 1983-08-19 | 1983-08-19 | Inverter circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6043080A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01221882A (en) * | 1988-03-01 | 1989-09-05 | Matsushita Electric Ind Co Ltd | High-frequency heating device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5858872A (en) * | 1981-10-01 | 1983-04-07 | Fuji Electron Component Kk | High frequency power generating circuit |
-
1983
- 1983-08-19 JP JP58151445A patent/JPS6043080A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5858872A (en) * | 1981-10-01 | 1983-04-07 | Fuji Electron Component Kk | High frequency power generating circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01221882A (en) * | 1988-03-01 | 1989-09-05 | Matsushita Electric Ind Co Ltd | High-frequency heating device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0572192B2 (en) | 1993-10-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6252781B1 (en) | Active reset forward converter employing synchronous rectifiers | |
| US9966837B1 (en) | Power converter with circuits for providing gate driving | |
| JPH05252737A (en) | Mosfet rectifying circuit for forward converter | |
| JPH0211178B2 (en) | ||
| WO2000041292A1 (en) | Self oscillating power converter circuit | |
| JPH09285120A (en) | Main switch control circuit of power source equipment | |
| JPS6322149B2 (en) | ||
| JP2000216671A (en) | MOSFET drive circuit | |
| JPH01202161A (en) | Snubber circuit | |
| JPH0572192B2 (en) | ||
| JP2918006B2 (en) | Boost type active filter circuit | |
| JP2882472B2 (en) | Power supply circuit using power insulated gate type FET | |
| JP3169873B2 (en) | Power supply | |
| GB2313495A (en) | Synchronous/driving circuit for a synchronous rectifier | |
| JPH01298949A (en) | Surge voltage suppressor circuit | |
| US12537446B2 (en) | Adaptive slew rate resonant power converter and conversion control circuit and control method thereof | |
| JP2586788Y2 (en) | MOS FET drive circuit | |
| JP4215408B2 (en) | Switching power supply | |
| JPH04588Y2 (en) | ||
| JPS6115523A (en) | Rush current suppressing circuit | |
| JPH03128673A (en) | Dc-dc converter | |
| JPS6026473A (en) | Self-excited inverter circuit | |
| JPH0430819Y2 (en) | ||
| JPS61273170A (en) | Clock control type dc-dc converter | |
| JP2002084745A (en) | Synchronous rectifying circuit of switching power supply |