JPH0572192B2 - - Google Patents
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- Publication number
- JPH0572192B2 JPH0572192B2 JP58151445A JP15144583A JPH0572192B2 JP H0572192 B2 JPH0572192 B2 JP H0572192B2 JP 58151445 A JP58151445 A JP 58151445A JP 15144583 A JP15144583 A JP 15144583A JP H0572192 B2 JPH0572192 B2 JP H0572192B2
- Authority
- JP
- Japan
- Prior art keywords
- source
- gate
- field effect
- effect transistor
- diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
- H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
- H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
- H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5383—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a self-oscillating arrangement
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は、開閉素子として用いた電界効果トラ
ンジスタ(以下MOSFETという)のターンオフ
時のスイツチング特性を改良したインバータ回路
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an inverter circuit with improved switching characteristics at turn-off of a field effect transistor (hereinafter referred to as MOSFET) used as a switching element.
[従来の技術]
MOSFETは高速度のターンオン、オフが可能
であるが、このドレイン、ソース間のターンオ
ン、オフはゲート、ソース間の電圧の立上り、立
下り速度に左右される。実際には、ゲート、ソー
ス間に比較的大きなキヤパシタンスCissが存在す
るので、この充電の速度がそのままMOSFETの
ターンオン、オフの速度を規制する。[Prior Art] MOSFETs can be turned on and off at high speed, but the turn on and off between the drain and the source depends on the rise and fall speed of the voltage between the gate and the source. In reality, there is a relatively large capacitance Ciss between the gate and source, so the charging speed directly regulates the turn-on and turn-off speed of the MOSFET.
また、制御電圧印加回路1とMOSFET2のゲ
ート間には、第1図に示すように、通常、寄生振
動防止用の小さな抵抗3を挿入する。この寄生振
動防止用抵抗3はMOSFET2のゲート、ソース
間のキヤパシタンスCissと制御電圧印加回路1と
の間の寄生振動を防止するためである。 Further, between the control voltage application circuit 1 and the gate of the MOSFET 2, as shown in FIG. 1, a small resistor 3 for preventing parasitic vibration is usually inserted. This parasitic vibration prevention resistor 3 is provided to prevent parasitic vibration between the gate-source capacitance Ciss of the MOSFET 2 and the control voltage application circuit 1.
[発明が解決しようとする問題点]
第1図において、トランジスタ4,5を挿入し
て折角MOSFET2のゲート、ソース間への電圧
の印加を早くしようとしても、前記寄生振動防止
用抵抗3によつてゲート、ソース間電圧Vgsの変
化速度は制限される。なお、第1図において、6
は主変圧器、7は2次側の整流平滑回路である。
また、抵抗3と並列のダイオードは、本発明によ
るもので、詳細な説明は後述する。[Problems to be Solved by the Invention] In FIG. 1, even if we try to speed up the voltage application between the gate and source of MOSFET 2 by inserting transistors 4 and 5, the parasitic vibration prevention resistor 3 Therefore, the rate of change of the gate-source voltage Vgs is limited. In addition, in Figure 1, 6
is the main transformer, and 7 is the rectifier and smoothing circuit on the secondary side.
Further, the diode in parallel with the resistor 3 is according to the present invention, and detailed explanation will be given later.
「問題点を解決するための手段]
本発明は、以上のような従来の問題点を解決す
るためになされたもので、電界効果トランジスタ
2と、主変圧器6を主体として構成され、前記電
界効果トランジスタ2を起動手段にて発振を開始
させて、直流電源をチヨツピングするインバータ
回路であつて、前記電界効果トランジスタ2のゲ
ート、ソース間に、前記主変圧器6に設けた補助
巻線9と抵抗10と飽和変圧器11からなる制御
電圧印加回路1を挿入し、この制御電圧印加回路
1の飽和変圧器11の2次巻線13の一端と前記
電界効果トランジスタ2のゲート間に、寄生振動
防止用の小さな抵抗3を挿入してなるインバータ
回路において、前記抵抗3と並列に、前記電界効
果トランジスタ2のゲート方向にアノードが向く
ようにしてダイオード14を挿入し、前記飽和変
圧器11の2次巻線13の他端と前記電界効果ト
ランジスタ2のソース間に、前記電界効果トラン
ジスタ2のソース方向にアノードが向くようにし
てダイオード15を挿入し、このダイオード15
と並列にコンデンサ20を挿入してなることを特
徴とするインバータ回路である。"Means for Solving the Problems" The present invention has been made to solve the problems of the conventional art as described above, and is composed mainly of a field effect transistor 2 and a main transformer 6, This is an inverter circuit that starts oscillation of an effect transistor 2 using a starting means to trip a DC power supply, and includes an auxiliary winding 9 provided on the main transformer 6 between the gate and source of the field effect transistor 2. A control voltage application circuit 1 consisting of a resistor 10 and a saturation transformer 11 is inserted, and a parasitic vibration is generated between one end of the secondary winding 13 of the saturation transformer 11 of the control voltage application circuit 1 and the gate of the field effect transistor 2. In an inverter circuit formed by inserting a small resistor 3 for prevention, a diode 14 is inserted in parallel with the resistor 3 with its anode facing toward the gate of the field effect transistor 2, and the 2 of the saturation transformer 11 is A diode 15 is inserted between the other end of the next winding 13 and the source of the field effect transistor 2, with the anode facing toward the source of the field effect transistor 2.
This is an inverter circuit characterized in that a capacitor 20 is inserted in parallel with the inverter circuit.
[作用]
本発明のダイオード14を抵抗3の両端に結合
すると、振動は抵抗3によつて阻止され、かつゲ
ート、ソース間電圧Vgsの変化の速度を極限まで
高めることが可能である。すなわち、まず、飽和
変圧器11の飽和および電圧の降下は従来例と同
様であるが、ゲート、ソース間の電荷Cissはダイ
オード14を通じて急速に放電され、急峻な放電
電流が流れ、これによりゲート、ソース間電圧は
急速に低下し、これによりドレイン、ソース間電
圧は急速に電圧を負担し始め、従来方式よりも著
しくそのスイツチング特性を改善するものであ
る。[Function] When the diode 14 of the present invention is coupled to both ends of the resistor 3, vibrations are prevented by the resistor 3, and it is possible to increase the speed of change of the gate-source voltage Vgs to the maximum. That is, first, the saturation and voltage drop of the saturation transformer 11 are the same as in the conventional example, but the charge Ciss between the gate and the source is rapidly discharged through the diode 14, and a steep discharge current flows, which causes the gate, The source-to-source voltage drops rapidly, and the drain-to-source voltage quickly begins to bear the load, which significantly improves the switching characteristics over the conventional system.
[実施例]
以下、本発明によるMOSFETを用いたインバ
ータ回路の実施例を第2図以下の図面に基づいて
説明する。[Example] Hereinafter, an example of an inverter circuit using MOSFETs according to the present invention will be described based on the drawings starting from FIG.
第2図は本発明によるフオワード型の基本的回
路図を示し、第3図は第2図の具体的回路図を示
すものである。これらの図において、+、−は正負
の直流入力電源端子で、一方の電源端子+から主
変圧器6の1次巻線8、MOSFET2のドレイ
ン、ソースを経て他方の電源端子−に結合されて
いる。また、前記MOSFET2のゲート、ソース
端子には、制御電圧印加回路1が結合されてい
る。この制御電圧印加回路1は、前記主変圧器6
に設けられた補助巻線9の両端に、抵抗10を介
して飽和変圧器11の1次巻線12の両端を結合
し、また、飽和変圧器11の2次巻線13の一端
は、抵抗13を介してMOSFET2のゲートに結
合し、他端は、MOSFET2のソースに結合され
て構成されている。 FIG. 2 shows a basic circuit diagram of the forward type according to the present invention, and FIG. 3 shows a specific circuit diagram of FIG. 2. In these figures, + and - are positive and negative DC input power supply terminals, which are connected from one power supply terminal + to the other power supply terminal - through the primary winding 8 of the main transformer 6, the drain and source of MOSFET 2. There is. Furthermore, a control voltage application circuit 1 is coupled to the gate and source terminals of the MOSFET 2. This control voltage application circuit 1 includes the main transformer 6
Both ends of the primary winding 12 of the saturation transformer 11 are connected via a resistor 10 to both ends of the auxiliary winding 9 provided at the 13 to the gate of MOSFET 2, and the other end is connected to the source of MOSFET 2.
そして、本発明では、特に、前記抵抗3と並列
に、MOSFET2のゲート方向にアノードが向く
ようにダイオード14が挿入されている。 In the present invention, in particular, a diode 14 is inserted in parallel with the resistor 3 so that its anode faces toward the gate of the MOSFET 2.
また、前記飽和変圧器11の2次巻線13と
MOSFET2のソース間に、ダイオード15を挿
入し、このダイオード15のカソード側と前記正
側端子+との間に、抵抗16と、補助巻線17で
開閉される電子的開閉素子18からなり、起動後
に起動側の影響を消滅させる手段19を結合す
る。また、前記ダイオード15と並列に、前記ゲ
ート、ソース間の電荷Cissより大きな容量のコン
デンサ20を結合するとともに、補助巻線21で
開閉される電子的開閉素子22からなり、起動後
のダイオード15の電圧を消滅させる手段23を結
合する。 Further, the secondary winding 13 of the saturation transformer 11 and
A diode 15 is inserted between the sources of MOSFET 2, and between the cathode side of this diode 15 and the positive side terminal +, there is a resistor 16 and an electronic switching element 18 that is opened and closed by an auxiliary winding 17. A means 19 for eliminating the influence of the activation side is added later. Further, a capacitor 20 having a capacitance larger than the charge Ciss between the gate and the source is coupled in parallel with the diode 15, and an electronic switching element 22 that is opened and closed by an auxiliary winding 21 is connected in parallel to the diode 15 after startup. Means 23 for extinguishing the voltage are coupled.
前記主変圧器6の2次巻線24には、整流平滑
回路7、誤差増幅回路25を介して出力端子2
6,27が結合されている。 The secondary winding 24 of the main transformer 6 is connected to the output terminal 2 via a rectifying and smoothing circuit 7 and an error amplifying circuit 25.
6 and 27 are combined.
つぎに、第3図の回路の作用を第5図の正常運
転時の波形図により説明する。 Next, the operation of the circuit shown in FIG. 3 will be explained with reference to the waveform diagram during normal operation shown in FIG.
まず、飽和変圧器11による自励発振動作の概
略を説明する。 First, an outline of the self-oscillation operation by the saturation transformer 11 will be explained.
起動時は、電子的開閉素子18をオンすると、
正側端子+→電子的開閉素子18→抵抗16→飽
和変圧器11の2次巻線13→抵抗3→
MOSFET2のゲート、ソース→負側端子−の回
路が形成される。すると、MOSFET2がオンし
て、正側端子+→主変圧器6の1次巻線8→
MOSFET2のドレイン、ソース→負側端子−の
回路が形成されて起動する。 At startup, when the electronic switching element 18 is turned on,
Positive side terminal + → electronic switching element 18 → resistor 16 → secondary winding 13 of saturation transformer 11 → resistor 3 →
A circuit from the gate and source of MOSFET2 to the negative terminal is formed. Then, MOSFET 2 turns on, and the positive terminal + → primary winding 8 of main transformer 6 →
A circuit from the drain and source of MOSFET2 to the negative terminal is formed and starts up.
起動後、主変圧器6の補助巻線17の誘起電圧
により電子的開閉素子18がオフ→主変圧器6の
1次巻線8→MOSFET2のドレイン、ソース→
負側端子−へとドレイン電流がながれる。 After startup, the electronic switching element 18 is turned off by the induced voltage in the auxiliary winding 17 of the main transformer 6 → the primary winding 8 of the main transformer 6 → the drain and source of MOSFET 2 →
Drain current flows to the negative terminal.
つぎに、第3図の主変圧器6の補助巻線9より
電圧V9が取り出されて、電流制限抵抗10を介
して飽和変圧器11に供給される。飽和変圧器1
1の2次巻線13は、抵抗3を介してMOSFET
2のゲート、ソース間に結ばれているので、第5
図のT1,T2間においては前記電圧V9が飽和変圧
器11を介してゲート、ソース間電圧Vgsとして
印加され、MOSFET2の導通が保持されてい
る。なお、導通中、ゲート電流Igはほとんど流れ
ていないので、
V9≒Vgsと考えても差支えない。 Next, voltage V 9 is taken out from auxiliary winding 9 of main transformer 6 in FIG. 3 and supplied to saturation transformer 11 via current limiting resistor 10. saturation transformer 1
The secondary winding 13 of 1 is connected to the MOSFET through the resistor 3.
Since it is connected between the gate and source of No. 2, the fifth
Between T 1 and T 2 in the figure, the voltage V 9 is applied as the gate-source voltage Vgs via the saturation transformer 11, and the conduction of the MOSFET 2 is maintained. Note that since almost no gate current Ig flows during conduction, it is safe to assume that V 9 ≈Vgs.
T2時に近くになつて飽和変圧器11が一定電
圧時間積を受けると、この飽和変圧器11は飽和
する。飽和すると、飽和変圧器11は短絡された
と同様になるので、ゲート、ソース間電圧Vgsは
失つてT2時において遮断される。この飽和時、
補助巻線9からの電流は、電流制限抵抗10によ
つて制限される。 Near time T 2 , when the saturation transformer 11 experiences a constant voltage-time product, the saturation transformer 11 becomes saturated. When saturated, the saturation transformer 11 becomes as if it were short-circuited, so the gate-source voltage Vgs is lost and it is cut off at T2 . At this saturation,
The current from the auxiliary winding 9 is limited by a current limiting resistor 10.
T2−T3間、MOSFET2は遮断されたままであ
るが、主変圧器6がMOSFET2の導通時(T1−
T2時)に受けとつたときと等量の一定電圧時間
積を受けてT3時に至ると反転を開始し、ゲート、
ソース間電圧Vgsは正電圧となり、これが
MOSFET2のゲートしきい値電圧を越え、ター
ンオンし、導通を開始し、以下同様にして発振動
作を繰返す。 During T 2 - T 3 , MOSFET 2 remains cut off, but when the main transformer 6 turns on MOSFET 2 (T 1 -
When it receives a constant voltage time product of the same amount as that received at T 2 o'clock) and reaches T 3 o'clock, inversion starts, and the gate,
The source-to-source voltage Vgs becomes a positive voltage, which
When the gate threshold voltage of MOSFET2 is exceeded, it turns on and starts conducting, and the oscillation operation is repeated in the same manner.
つぎに、本発明のダイオード14のない従来回
路の場合のターン、オフ時の各部の動作を第6図
によつて説明する。 Next, the operation of each part during turn-on and off-time in the case of the conventional circuit without the diode 14 of the present invention will be explained with reference to FIG.
まず、飽和変圧器11がt1時に飽和して短絡状
態になると、飽和変圧器11は急速にその電圧
V11が消滅する。しかし、抵抗3に妨げられて
MOSFET2のゲート、ソース間に蓄えられてい
た電荷Cissは有限の電流Igとなつて抵抗3、飽和
変圧器11の2次巻線13、コンデンサ20を流
れ、これによつてゲート、ソース間電圧Vgsは第
6図の1点鎖線にように比較的ゆつくりした速度
で下降を始める。T2時に至り、ゲート、ソース
間電圧Vgsがゲートしきい値電圧以下になるとド
レイン、ソース間は電圧Vdsを負担し始める。つ
まりターンオフを開始する。以下、このゲート、
ソース間電圧Vgsの低下に追従してドレイン、ソ
ース間電圧Vdsは増加しt3時に至り、ターンオフ
は完了する。 First, when the saturation transformer 11 becomes saturated and short-circuited at time t 1 , the saturation transformer 11 rapidly increases its voltage.
V 11 disappears. However, due to resistance 3,
The charge Ciss stored between the gate and source of MOSFET 2 becomes a finite current Ig and flows through the resistor 3, the secondary winding 13 of the saturation transformer 11, and the capacitor 20, thereby increasing the voltage Vgs between the gate and source. begins to descend at a relatively slow speed, as shown by the dashed-dotted line in Figure 6. At T2 , when the voltage Vgs between the gate and the source becomes less than the gate threshold voltage, the voltage Vds begins to be applied between the drain and the source. In other words, start turning off. Below, this gate,
Following the decrease in the source voltage Vgs, the drain-source voltage Vds increases and reaches time t3 , at which point turn-off is completed.
以上の説明のように、ドレイン、ソース間電圧
Vdsの増加の速度、つまりターンオフ速度はゲー
ト、ソース間電圧Vgsの変化に比例する。このた
め、抵抗3を小さくすることが望ましい。しか
し、この抵抗3は、ゲート、ソース間のキヤパシ
タンスCissとの間の振動を阻止するために一定容
量以上が必要である。 As explained above, the drain-source voltage
The speed of increase in Vds, that is, the turn-off speed, is proportional to the change in the gate-source voltage Vgs. For this reason, it is desirable to make the resistance 3 small. However, this resistor 3 needs to have a certain capacity or more in order to prevent vibration between the gate and the source capacitance Ciss.
つぎに、本発明では、ダイオード14を抵抗3
の両端に結合したので、振動は抵抗3によつて阻
止され、しかも、ゲート、ソース間電圧Vgsの変
化の速度を極限まで高めることが可能である。以
上の状況を第7図によつて説明する。 Next, in the present invention, the diode 14 is connected to the resistor 3.
Since the resistor 3 is coupled to both ends of the resistor 3, vibrations are prevented by the resistor 3, and the speed of change in the gate-source voltage Vgs can be increased to the maximum. The above situation will be explained with reference to FIG.
まず、t1時での飽和変圧器11の飽和および電
圧V11の降下は、第6図の従来例と同様である。
しかし、本発明では、MOSFET2のゲート、ソ
ース間の電荷Cissは、ダイオード14を通じて、
飽和変圧器11の2次巻線13、コンデンサ20
の回路により急速に放電され、第7図のt1,t2,
t3間のゲート電流のような急峻な放電電流が流
れ、これによりゲート、ソース間電圧Vgsは急速
に低下し、これによりドレイン、ソース間電圧
Vdsは急速に電圧を負担し始め、従来方式よりも
著しくそのスイツチング特性を改善するものであ
る。ちなみに第7図のt2〜t3間の電流Idcはドレイ
ン、ソース間のキヤパシタンス20の充電時のも
のであり、これはターンオン時に電源に返還され
るので、電力損失は形成せず、全体に能率も甚し
く改善される。ここで、コンデンサ20の容量
は、MOSFET2のゲート、ソース間の電荷Ciss
よりも大きいことが必要である。 First, the saturation of the saturation transformer 11 and the drop in the voltage V11 at time t1 are the same as in the conventional example shown in FIG.
However, in the present invention, the charge Ciss between the gate and source of MOSFET 2 is transferred through the diode 14.
Secondary winding 13 of saturation transformer 11, capacitor 20
It is rapidly discharged by the circuit of t 1 , t 2 ,
A steep discharge current similar to the gate current between t3 flows, which causes the gate-source voltage Vgs to drop rapidly, which causes the drain-source voltage to drop.
Vds begins to bear the voltage rapidly, which improves its switching characteristics significantly over the conventional method. By the way, the current Idc between t 2 and t 3 in Figure 7 is when the capacitance 20 between the drain and the source is charged, and this is returned to the power supply at turn-on, so no power loss occurs and the overall Efficiency is also greatly improved. Here, the capacitance of the capacitor 20 is the charge Ciss between the gate and source of MOSFET 2.
It needs to be larger than .
なお、本発明はターンオン時の改善には作用し
ないが第3図、第4図のように出力側で電力、電
圧の制御が行なわれるコンバータにおいては、タ
ーンオン時のドレイン電流は零であることと相俟
つて、ターンオフ時のみの改善で回路全体として
は充分である。このことは第1図のフライバツク
方式においてもターンオン電流はほとんど零であ
るので、抵抗3と並列にダイオード14を挿入す
ることにより、上述の場合と同様に、ターンオフ
時の効果が得られる。 Although the present invention does not improve turn-on, in converters where power and voltage are controlled on the output side as shown in Figures 3 and 4, the drain current at turn-on is zero. In combination, the improvement only at turn-off is sufficient for the entire circuit. This means that even in the flyback system shown in FIG. 1, the turn-on current is almost zero, so by inserting the diode 14 in parallel with the resistor 3, the same effect at turn-off as in the above case can be obtained.
本発明は第4図に示すような2個のMOSFET
2a,2bをプツシユプル結合した場合もそのま
ま利用でき、その作用も前述と略同様である。 The present invention uses two MOSFETs as shown in Figure 4.
Even when 2a and 2b are coupled in a push-pull manner, it can be used as is, and its operation is substantially the same as described above.
[発明の効果]
(1) 電界効果トランジスタ2のゲート、ソース間
に蓄えられた電荷Cissは、抵抗3を介すること
なく、ダイオード14、飽和変圧器11の2次
巻線13、コンデンサ20を介して放電するの
で、ターンオフ時のスイツチング特性を著しく
改善することができる。特に、開閉素子として
電界効果トランジスタ2を用いた超高周波のイ
ンバータ回路に最も効果的に作用し、この発振
周波数を電界効果トランジスタ2の特性の限界
まで利用して1000〜1500KHzの超高周波コンバ
ータを、能率の低下をみることなく達成させる
ことが可能である。[Effects of the Invention] (1) The electric charge Ciss accumulated between the gate and source of the field effect transistor 2 is transferred through the diode 14, the secondary winding 13 of the saturation transformer 11, and the capacitor 20, without passing through the resistor 3. The switching characteristics at turn-off can be significantly improved. In particular, it works most effectively on ultra-high frequency inverter circuits that use field effect transistors 2 as switching elements, and utilizes this oscillation frequency to the limit of the characteristics of field effect transistors 2 to create ultra high frequency converters of 1000 to 1500 KHz. This can be achieved without any decrease in efficiency.
(2) コンデンサ20に充電された電荷は、電界効
果トランジスタ2のターンオン時に電源に返還
されるので、電力損失は形成せず、全体に能率
も甚しく改善される。(2) Since the electric charge charged in the capacitor 20 is returned to the power source when the field effect transistor 2 is turned on, no power loss occurs and the overall efficiency is greatly improved.
(3) 寄生振動防止用抵抗3と並列に、ダイオード
14を挿入するとともに、飽和変圧器11の2
次巻線13の他端と電界効果トランジスタ2の
ソース間に、電界効果トランジスタ2のソース
方向にアノードが向くようにしてダイオード1
5を挿入し、このダイオード15と並列にコン
デンサ20を挿入しただけなので、部品点数を
わずかに増やすだけで初期の目的が達成でき、
ほとんどコストアツプになることはない。(3) Insert a diode 14 in parallel with the parasitic vibration prevention resistor 3, and
A diode 1 is connected between the other end of the next winding 13 and the source of the field effect transistor 2 with the anode facing toward the source of the field effect transistor 2.
5 and a capacitor 20 in parallel with this diode 15, the initial purpose can be achieved with only a slight increase in the number of components.
There is almost no cost increase.
第1図はMOSFETを用いたフライバツク型の
インバータ回路図、第2図はフオワード型のイン
バータ回路の基本的電気回路図、第3図は本発明
によるインバータ回路の基本的電気回路図、第4
図は本発明の他の実施例の電気回路図、第5図は
は自励発振時における出力波形図、第6図は従来
回路におけるターンオフ時の時間軸を拡大した波
形図、第7図は本発明におけるターンオフ時の時
間軸を拡大した波形図である。
1……制御電圧印加回路、2,2a,2b……
MOSFET、3,3a,3b……抵抗、6……主
変圧器、7……整流平滑回路、9……補助巻線、
10……抵抗、11……飽和変圧器、14,14
a,14b……ダイオード。
Figure 1 is a flyback type inverter circuit diagram using MOSFETs, Figure 2 is a basic electric circuit diagram of a forward type inverter circuit, Figure 3 is a basic electric circuit diagram of an inverter circuit according to the present invention, and Figure 4 is a basic electric circuit diagram of a forward type inverter circuit.
Figure 5 is an electric circuit diagram of another embodiment of the present invention, Figure 5 is an output waveform diagram during self-excited oscillation, Figure 6 is a waveform diagram with the time axis enlarged at turn-off in the conventional circuit, and Figure 7 is FIG. 3 is a waveform diagram showing an enlarged time axis during turn-off in the present invention. 1... Control voltage application circuit, 2, 2a, 2b...
MOSFET, 3, 3a, 3b...resistance, 6...main transformer, 7...rectifier smoothing circuit, 9...auxiliary winding,
10...Resistor, 11...Saturation transformer, 14,14
a, 14b...Diode.
Claims (1)
体として構成され、前記電界効果トランジスタ2
を起動手段にて発振を開始させて、直流電源をチ
ヨツピングするインバータ回路であつて、前記電
界効果トランジスタ2のゲート、ソース間に、前
記主変圧器6に設けた補助巻線9と抵抗10と飽
和変圧器11からなる制御電圧印加回路1を挿入
し、この制御電圧印加回路1の飽和変圧器11の
2次巻線13の一端と前記電界効果トランジスタ
2のゲート間に、寄生振動防止用の小さな抵抗3
を挿入してなるインバータ回路において、前記抵
抗3と並列に、前記電界効果トランジスタ2のゲ
ート方向にアノードが向くようにしてダイオード
14を挿入し、前記飽和変圧器11の2次巻線1
3の他端と前記電界効果トランジスタ2のソース
間に、前記電界効果トランジスタ2のソース方向
にアノードが向くようにしてダイオード15を挿
入し、このダイオード15と並列にコンデンサ2
0を挿入してなることを特徴とするインバータ回
路。1 Mainly composed of a field effect transistor 2 and a main transformer 6, the field effect transistor 2
The inverter circuit starts oscillation by a starting means and chops the DC power supply, and the inverter circuit includes an auxiliary winding 9 and a resistor 10 provided on the main transformer 6 between the gate and source of the field effect transistor 2. A control voltage application circuit 1 consisting of a saturation transformer 11 is inserted, and a parasitic vibration prevention circuit is installed between one end of the secondary winding 13 of the saturation transformer 11 of the control voltage application circuit 1 and the gate of the field effect transistor 2. small resistance 3
In the inverter circuit, a diode 14 is inserted in parallel with the resistor 3 with its anode facing toward the gate of the field effect transistor 2, and a diode 14 is inserted in the secondary winding 1 of the saturation transformer 11.
A diode 15 is inserted between the other end of the field effect transistor 3 and the source of the field effect transistor 2, with the anode facing toward the source of the field effect transistor 2, and a capacitor 2 is connected in parallel with the diode 15.
An inverter circuit characterized by inserting 0.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58151445A JPS6043080A (en) | 1983-08-19 | 1983-08-19 | Inverter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58151445A JPS6043080A (en) | 1983-08-19 | 1983-08-19 | Inverter circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6043080A JPS6043080A (en) | 1985-03-07 |
| JPH0572192B2 true JPH0572192B2 (en) | 1993-10-08 |
Family
ID=15518752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58151445A Granted JPS6043080A (en) | 1983-08-19 | 1983-08-19 | Inverter circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6043080A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2624283B2 (en) * | 1988-03-01 | 1997-06-25 | 松下電器産業株式会社 | High frequency heating equipment |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5858872A (en) * | 1981-10-01 | 1983-04-07 | Fuji Electron Component Kk | High frequency power generating circuit |
-
1983
- 1983-08-19 JP JP58151445A patent/JPS6043080A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6043080A (en) | 1985-03-07 |
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