JPS6043693B2 - drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a drive circuit using MOS transistors.

A drive circuit made of MOS transistors used for driving word lines of a memory is generally configured as shown in FIG.

That is, an input signal is supplied to the gate of the driving MOS transistor Q through an inverter 11, and the MOS transistor Q serves as a load resistor. The device has a push-pull configuration in which the input signal is directly supplied to the device. Usually, an enhancement (E) type is used as the drive MOS transistor Q1, but either an E type or a depletion (D) type can be used as the load MOS transistor Q2. By the way, the load MOS transistor Q.

When is of type E, there are disadvantages in that the signal propagation speed (rise) is slow and a sufficient output level cannot be obtained when the output is active (``1''). On the other hand, MO for load
When the S transistor Q2 is a D type, the propagation speed is fast;
Although the ``1'' level is sufficient, the problem is that the power consumption at ``0'' is large. Memory word line drive circuits are required as many as the number of word lines, and in this case, out of the multiple drive circuits, normally only one of the multiple drive circuits outputs “1”.
The remaining number is 1'"o".

Also, since the power consumption of a drive circuit with an output of ``0'' is larger than that with an output of ``1'', when many drive circuits are lined up, the overall power consumption is extremely large. becomes. Therefore, although the propagation speed is also important, especially for a word line drive circuit of a memory, the larger the scale of the memory, the lower the power consumption is desired. This invention has been made in view of the above points, and is useful for word line driving of memory, which reduces power consumption without impairing propagation speed, and provides a sufficient output level. A drive circuit using MOS transistors is provided. An example of a drive circuit according to the present invention is shown in FIG.

The driving MOS transistor Qll is an n-channel E type, and has an inverter 111 interposed between its gate and input terminal. The load resistance is two n-channel MOS
Transistors Q2l, Q2. are connected in parallel, and their gates are commonly connected to the input terminal. Among these load MOS transistors Q2l and Q22, one MOS transistor Q2l has a large channel width.
The other MOS transistor Q22 is a D type with a small channel width.
Due to the inclusion of transistor Q22, the output ゜“
A level of 1 is large enough.

The power consumption at "0" can be made sufficiently small by reducing the channel width of this D-type MOS transistor Q22.
Although the propagation speed is reduced by reducing the size of the OS transistor Q22, this can be recovered by increasing the channel width of the other E-type MOS transistor Q2l. That is, a sufficiently large output level can be obtained without reducing the propagation speed, and power consumption can also be reduced. The above is done using the time chart in Figure 3. The explanation is as follows.

As shown in the figure, when a step-like "1" signal is input to the input terminal Vi, the D-type MOS transistor Q as a load
If only 22 is considered, the voltage at the output terminal VO will be as shown by curve A. In other words, ζ, which has a slow rise due to its small dimensions, reaches a sufficient level of ゜1゛ in a steady state.On the other hand, the E-type M
When only the OS transistor Q2l is considered, a sufficient output level is not produced as shown in curve B, but the rise is fast due to the increased dimensions. Therefore, in an actual circuit in which the D-type MOS transistor Q22 and the E-type MOS transistor Q2l are connected in parallel, the rise is fast as shown by curve C, and a sufficient level of ゜1゛ output can be obtained. In Figure 2, the load MOS transistor Q
2l, Q2.

are shown separately, but when actually constructed as an integrated circuit, they can be made integrally, and the structure can be made almost the same as in the conventional case shown in FIG.
This type of MOS transistor Q2. and E-type MOS
To integrally configure the transistor Q2l, see Figure 4a-
You can do it like c. FIG. 4a is a schematic planar pattern, and FIGS. 4B and 4c are cross-sectional views taken along the line 1--V1--1 of section a, respectively. That is, using a p-type Si substrate 1, an n+ type source region 2 and a drain region 3 are formed, and a gate oxide film and a polycrystalline silicon gate electrode 5 are provided to form an E-type n-channel MOS transistor. And a MOS like this
An n-type inversion layer 6 is formed by, for example, ion implantation in a region other than both end portions of the channel region of the transistor, thereby forming a channel region of a D-type channel MOS transistor. 7
8 is a field oxide film, 8 is a CVD oxide film, and 9 is an aluminum electrode, and these structures are obtained by a well-known method.

In this way, the two load MOS transistors Q2l, Q
22 is integrally formed in one ordinary MOS transistor region, sharing the source region, drain region, and gate electrode.

The power consumption can be reduced by reducing the width of the n-type inversion layer 6, and the propagation speed can be made sufficiently high by increasing the overall channel width. In addition, by providing a margin at both ends of the channel region of the E type MOS transistor, D
Since the channel region of the D-type MOS transistor is provided, the channel width of the D-type MOS transistor can be reliably determined by the mask accuracy even if there is a misalignment due to mask alignment during ion implantation, etc., and therefore the load can be maintained as designed. characteristics can be realized reliably. Therefore, the load side rise characteristics of the drive circuit can be realized as designed.
It is extremely effective as a memory word line drive circuit. In addition,
This invention is not limited to the above-mentioned embodiments, but can be modified in various ways.

For example, the dimensions of a D-type MOS transistor and an E-type MOS transistor used in parallel connection as a load resistor can be appropriately selected depending on characteristics such as speed and power consumption required of the drive circuit.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a drive circuit using conventional MOS transistors, FIG. 2 is a diagram showing an example of a drive circuit according to the present invention, and FIG. 3 is a time chart for explaining its operating characteristics. Figures 4a-c are load MOs in Figure 2.
In an example in which S transistors Q2l and Q22 are integrally configured, a is a schematic plan view, and B and c are IV, 1-2'' cross-sectional views of a, respectively. Qll... Drive MOS Transistor (.

Claims (1)

[Claims] 1 A driver consisting of an E-type MOS transistor, an E-type MOS transistor with the same conductive channel, and a D-type M
A drive circuit comprising a load in which OS transistors are connected in parallel, and a voltage having a polarity opposite to the voltage applied to the gate of each MOS transistor as the load is applied to the gate of the E-type MOS transistor as the driver. ,
The E-type MOS transistor as the load is constructed by providing source and drain regions of opposite conductivity types separated from each other in a semiconductor layer of one conductivity type, and providing a gate electrode on a channel region between these two regions with a gate insulating film interposed therebetween. and the D-type MO
The S transistor shares a source/drain region and a gate electrode with the source/drain region and gate electrode of the E-type MOS transistor serving as the load, respectively, and a channel region of the E-type MOS transistor serving as the load. A drive circuit comprising a layer of a conductivity type opposite to that of the semiconductor layer locally provided in a region excluding both ends in the width direction.