JPH0555491A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] To provide a semiconductor device provided with a sense amplifier which has no operational offset and has high stability and excellent symmetry in operation. In a semiconductor device having a sense amplifier including an impurity region formed by ion implantation tilted from an axis perpendicular to a substrate surface and including at least one pair of transistors connected to a pair of data lines, at least the data The transistor pairs are arranged such that a parasitic resistance due to the ion implantation occurring in a pair of transistors to which the line pair is connected occurs in electrodes of the same kind in a circuit. [Effect] Parasitic resistance due to the offset region generated in the input transistor of the sense amplifier becomes a circuit target,
It is possible to realize a semiconductor device including a sense amplifier having high stability and symmetry that does not cause asymmetry in operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a method for arranging a sense amplifier.

[0002]

2. Description of the Related Art Generally, when an impurity region is formed on a silicon substrate having a crystal orientation of, for example, 100 by using an ion implantation method, it is not vertical to the silicon substrate in order to suppress a defect due to a tunneling effect. Ion implantation is performed with the mark attached.
FIG. 4 is a diagram showing a cross-sectional structure of a MOS transistor arranged such that the channel direction is parallel to the direction in which the above-mentioned angular offset occurs. The transistor in this Figure 4 is an LD
This is an N-channel transistor having a D (Lightly-Doped-Drain) structure, and the regions 8 and 9 having a low N-type impurity concentration are ion-implanted using the gate electrode 1 made of, for example, polysilicon as a mask, and then the sidewalls 2 and 3 to form N-type high-concentration impurity regions 10 and 1
It is formed by implanting 1. Here, the source electrode or the drain electrode of the MOS transistor is taken out from the impurity region 10 or 11, respectively. Since these ion implantations are not performed perpendicularly to the silicon substrate, the thin impurity region 8 shifts from the left end of the gate electrode 1 toward the high-concentration impurity region 10 side, and the gate electrode and the N-type impurity region overlap at the left end of the channel. An offset region 12 that does not occur occurs. FIG. 5 shows an equivalent circuit when the high-concentration impurity region 10 of the N-channel transistor shown in FIG. 4 is used as the source electrode. As shown in FIG. 5, the offset region 12 equivalently becomes a parasitic resistance, and is configured to be connected in cascade between the source terminal S2 of the ideal transistor and the source electrode ST2 taken out from the high concentration impurity region 10.

FIG. 3 is a layout diagram of a sense amplifier of a conventional semiconductor device, and is an example of a current mirror type sense amplifier. In FIG. 3, only a field layer, a polysilicon layer, a contact layer and a metal wiring layer are shown. Transistors T1 and T2 are P-channel transistors which are active loads of sense amplifiers, and transistors T3 and T4 are complementary input signals VIN, N to which VINB is connected
The channel transistor and the transistor T5 are the signal CLK
Is an N-channel transistor for controlling activation of the sense amplifier. Here, the ion implantation is performed with an inclination from the direction indicated by the arrow ID in FIG.

FIG. 6 is an equivalent circuit of the sense amplifier shown in FIG. 3, in which parasitic resistances such as diffusion resistance, contact resistance, polysilicon resistance and metal wiring resistance are omitted. In the sense amplifier layout of FIG. 3, transistors T3, T
4 has a channel direction parallel to the ion implantation direction ID indicated by an arrow in FIG. 3, and parasitic resistances RL3 and RL4 caused by the offset region are connected to the source end of the transistor T3 and the drain end of the transistor T4, respectively. Will be done.

In the sense amplifier equivalent circuit of FIG. 6, for example, a bit line pair for outputting a minute amplitude signal from a memory cell is connected to the input terminals VIN and VINB, the potential of which is about half of the power supply voltage, and the amplitude thereof. It is about 100 millivolts to several hundred millivolts. Here, a positive logic signal is connected to VIN, and a signal having a complementary logic to VIN is connected to VINB. In addition, when the signal CLK becomes High and the sense amplifier is activated, VIN, VINB
Although the transistors T3 and T4 connected to each other are both in a conductive state, a difference in ON resistance occurs depending on the potentials of VIN and VINB, so that the sense amplifier output VOUT has V
A signal amplified according to the potentials of IN and VINB is output.

[0006]

Since the conventional semiconductor device is constructed as described above, it has the following problems.

It is assumed that one input VIN is logically High.
When a low level is logically input to the other input VINB, the transistors T1 and T3 are connected from the power supply line.
A current flows into the drain terminal D5 of the transistor T5 via the, and a voltage drop occurs in the parasitic resistance RL3. Since the gate-source voltage that determines the capability of the transistor T3 is not the voltage between the input VIN and the drain terminal D5 of the transistor T5, but is effectively the voltage between the input VIN and the source terminal S3, the voltage drop across the parasitic resistance RL3. The capacity of the transistor T3 is reduced accordingly, and the on-resistance is increased. Therefore, the gate terminal G2 of the P-channel transistor T2 which is the active load of the sense amplifier
The electric potential of increases and its ability decreases. On the other hand, since the parasitic resistance does not occur on the source terminal side of the transistor T4, the effective gate-source voltage becomes the voltage between the input VINB and the drain terminal D5 of the transistor T5, and the parasitic resistance does not reduce the capacity. Therefore, the potential of the output VOUT, which originally desires a high voltage potential, drops due to a decrease in the capability of the P-channel transistor T2 among the operations of the transistors T2 and T4.

Further, one input VIN is logically Low.
When the level is logically input to the other input VINB, a current flows from the power supply line to the drain terminal D5 of the transistor T5 through the transistors T1 and T3 as in the case described above, and the parasitic resistance RL3 is applied to the parasitic resistance RL3. Due to the voltage drop, the on resistance of the transistor T3 is increased and thus the capacity of the P-channel transistor T2 is also reduced. On the other hand, since the parasitic resistance does not occur on the source terminal side of the transistor T4, the capacity does not decrease. Therefore, the potential of the output VOUT, which originally desires a low voltage potential, becomes even lower due to the operation of the transistors T2 and T4.

As described above, even if a signal having any logic state is input, a signal having a logic level High is output to the sense amplifier output VOUT, which is a signal shifted to the low voltage side, that is, having an offset. When input, the amplification degree decreases, and when a signal of logic level Low is input, the amplification degree increases, and the amplification degree of the sense amplifier decreases overall. Further, due to the above-mentioned output offset, even if there is almost no potential difference between VIN and VINB, for example, even when the memory circuit starts outputting information from the memory cell, a logically low level signal is output to the output VOUT. Therefore, there is a risk that the amplification speed of the sense amplifier is slowed down or a malfunction occurs in the initial stage of the amplification operation.

In a typical conventional sense amplifier design example,
Since the parasitic resistance RL3 was about 400 ohms and the current flowing through this resistance was about 500 microamperes, the voltage drop generated in the parasitic resistance RL3 was about 200 millivolts, and therefore the sense amplifier input signal had no signal amplitude of more than 200 millivolts. And had a serious problem of not starting normal operation.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device having a sense amplifier which has no operational offset and has high stability and excellent symmetry in operation. To do.

[0012]

The semiconductor device of the present invention comprises:
In a semiconductor device having a sense amplifier including a set of transistor pairs to which at least a data line pair is connected, an impurity region is formed by ion implantation performed at an angle from an axis perpendicular to the substrate surface, and at least the data line pair is In the semiconductor device, the transistor pair is arranged so that a parasitic resistance due to the ion implantation generated in a pair of connected transistors is generated in electrodes of the same kind in a circuit.

[0013]

In the semiconductor device of the present invention, the parasitic resistance in the sense amplifier due to the ion implantation angle is a circuit target, and the operation is also a target.

[0014]

FIG. 1 is a layout diagram of a sense amplifier showing an example of an embodiment according to the present invention and is an example of a layout diagram of a current mirror type sense amplifier. In FIG. 1, only a field layer, a polysilicon layer, a contact layer and a metal wiring layer are shown. Transistors T1 and T2 are P-channel transistors which are active loads of a sense amplifier, transistors T3 and T4 are complementary input signals VIN, The N-channel transistor to which VINB is connected, and the transistor T5 are N-channel transistors serving as switches for controlling activation of the sense amplifier by the signal CLK. Here, the ion implantation is performed with an inclination from the direction indicated by the arrow ID in FIG.

FIG. 2 is an equivalent circuit of the sense amplifier shown in FIG. 1, in which parasitic resistances such as diffusion resistance, contact resistance, polysilicon resistance and metal wiring resistance are omitted. In the sense amplifier layout of FIG. 1, with respect to the ion implantation direction ID, the transistor T3 is arranged so that the parasitic resistance RL1 caused by the offset region is generated on the drain side, and the transistor T4 is similarly arranged so that the parasitic resistance RL2 is generated on the drain side. There is.

The sense amplifier equivalent circuit of FIG. 2 has a parasitic resistance R on both drain sides of N-channel transistors T3 and T4.
This is a structure in which L1 and RL2 are connected, and achieves circuit symmetry. In addition, the N-channel transistor T3,
Since parasitic resistance is not connected to the source terminals of both T4,
The potential difference between VIN and S3 and between VINB and S4, which are the effective gate-source voltages of the respective transistors, does not decrease even if a signal of any logic state is input, and the amplification degree does not change due to the logic state. .. Therefore, there is no delay in the amplification speed due to the decrease in the amplification degree, which is a problem in the conventional device, and no malfunction occurs in the initial stage of the amplification operation.

In the embodiment of FIG. 1, the input transistor T
The parasitic resistance is generated on both drain sides of T3 and T4, but even if the parasitic resistance is generated on both source sides, the circuit symmetry is not lost. In addition, in the embodiment of FIG. 1, the input transistors T3 and T4, the active load P-channel transistors T1 and T2, and the switch transistor T5 are all arranged so as not to be affected by the ion implantation angle. Even if the channel direction of the transistor T5 is arranged so as to be parallel to the ion implantation direction ID, the operational symmetry of the sense amplifier is not impaired, and the channel directions of the P-channel transistors T1 and T2 are referred to as the ion implantation direction ID. Even if they are arranged in parallel, the effect on the circuit operation is that of the input transistor T
3, less serious than T4.

[0018]

As described above, according to the present invention, since the parasitic resistance caused by the offset region at the time of ion implantation generated in the input transistor of the sense amplifier is a circuit target, excellent stability and symmetry are achieved. A semiconductor device including the sense amplifier can be realized.

[Brief description of drawings]

FIG. 1 is a layout diagram of a sense amplifier of the present invention.

FIG. 2 is an equivalent circuit diagram of a sense amplifier of the present invention.

FIG. 3 is a layout diagram of a conventional sense amplifier.

FIG. 4 is a cross-sectional structure diagram of an LDD transistor.

FIG. 5 is an equivalent circuit diagram of an LDD transistor.

FIG. 6 is an equivalent circuit diagram of a conventional sense amplifier.

[Explanation of symbols]

T1, T2 ... Sense amplifier active load P-channel transistor T3, T4 ... Sense amplifier input N-channel transistor T5 ... Sense amplifier activation control N-channel transistor VIN, VINB ... Sense amplifier input signal VOUT ... -Sense amplifier output signal CLK ... Sense amplifier activation control signal ID ... Ion implantation direction RLDD, RL1, RL2, RL3, RL4 ... Parasitic resistance 1 ... Gate electrode 2, 3 ... Sidewall 4, 5, 8, 9 ... Thin N-type impurity regions 6, 7, 10, 11 ... Dark N-type impurity regions

Claims (1)

[Claims] 1. A semiconductor device having a sense amplifier including a set of transistor pairs to which at least data line pairs are connected, an impurity region is formed by ion implantation performed at an angle from an axis perpendicular to a substrate surface, and A semiconductor device, wherein the transistor pair is arranged such that a parasitic resistance due to the ion implantation generated in a pair of transistors to which the data line pair is connected occurs in electrodes of the same kind in a circuit.