JPS6045996A - Bipolar RAM - Google Patents

Abstract

PURPOSE:To expand the operation margine of a bipolar type RAM by switching a reading reference voltage in accordance with the number of memory cells to be read out. CONSTITUTION:When an operation mode control signal FS is in the low level and only one memory cell constituted by transistors (TRs) Q4, Q5 forming an FF by the cross coupling of word lines WO is to be read out, differential TRs Q1, Q2 in a current switching circuit are turned on and off respectively. consequently, constant current I1 does not flow into a resistor R1 and the readout reference voltage is determined by constant current IO flowing into the resistors R1, R2. When the signal FS is turned to the high level to read out many memory cells simultaneously, the constant current I1 also flows into the resitor R1 and the reading reference voltage is dropped. The same rule is applied also to other word lines and the simultaneous reading of plural blocks reduces the reference voltage as compared to the memory reading of one block, so that the level margine of the holding voltage of the memory cells is prevented from deterioration and the operation margine of the bipolar type RAM can be expanded.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a bipolar RAM, which constitutes an index array that identifies whether or not data to be processed is stored in a high-speed buffer memory in, for example, a large computer. The present invention relates to technology effective for high-speed bipolar RAM.

[Background technology]

In order to increase the processing speed of large-sized computers, a high-speed buffer memory that has a storage capacity equivalent to one memory block of the main memory and is composed of bipolar RAM is provided. By transferring the data in the main memory to be processed to this high-speed buffer memory and processing the data between the arithmetic unit and the Petza memory, high-speed processing is achieved. An index array (IA) is required to determine whether data to be processed (data at an address to be processed in the main memory) is stored in this buffer memory. This index array is written with an address signal corresponding to the main memory of the data stored in the buffer memory, and when the address signal is inputted, it outputs a detection signal indicating a comparison match.

In such an index memory, two types of read operation modes are provided. That is, one operation mode is an operation in which the data of one memory block (for example, n bits) is read out simultaneously, and the other operation mode is an operation in which data in all memory blocks (for example, n x 8 bits) is read out at the same time. be.

The inventor of the present application has revealed that the following problem occurs in a bipolar RAM having 21111 operating modes. That is, since the number of memory cells connected to a word line differs greatly depending on the two operation modes, the selection level of the word line fluctuates. This is because the read current for the memory cells is supplied through the word line drive circuit, and the current supplied from the word line drive circuit varies greatly depending on the number of memory cells to be read.

Therefore, the level margin of the holding voltage of the memory cell with respect to the subsequent reference voltage V ref of the memory cell deteriorates.

[Object of the Invention] An object of the present invention is to provide a bipolar RAM with an expanded operating margin.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

(Summary of the Invention) A brief overview of the typical inventions disclosed in this application is as follows.6 Namely, a memory cell that performs a continuation using an operation mode control signal. By switching the read reference voltage according to the number of memory cells, the holding voltage and the read reference voltage V r
This is to ensure a level margin with ef.

〔Example〕

FIG. 1 shows a schematic block diagram illustrating one implementation of a bipolar RAM according to the present invention. Each circuit block in the figure is formed on a single semiconductor substrate such as silicon by a known semiconductor integrated circuit manufacturing technique.

The memory array is composed of eight blocks BO to B7 as shown in the figure, although not particularly limited thereto. Each memory block BO to B7 has 1n word lines (64 in the figure) in the horizontal rows, and n pairs (7 pairs in the figure) of complementary data lines in the vertical columns. be done. The n-bit readout information from each of the blocks BO to B7 is supplied to one input of an exclusive OR circuit EX constituting a comparison match circuit via a column switch circuit. Further, the other input of this exclusive OR circuit EX is supplied with an address signal supplied from the outside. In this embodiment, a memory array and an exclusive OR circuit having the same configuration as described above are formed. Such a semiconductor integrated circuit is used in, for example, a large-sized computer sold by Hitachi, Ltd. under the trade name 'H-200Ha, and is well known, so a detailed explanation thereof will be omitted.

No. 21111 shows a specific main circuit diagram of an embodiment of the present invention.

In the figure, one memory cell, one word line drive circuit, a 1(lit) column switch circuit, etc. are shown as representatives.

The memory cell includes a driving npn transistor Q5, Q6 whose base and collector are cross-connected to each other, load resistors R4 and R5 respectively provided to the collector thereof, and each resistor R4 and R5 provided in parallel. clamp diode DI.

A flip-flop circuit configured with D2 is used.

The driving npn) transistor Q, 5.06 has a multi-emitter structure, although it is not particularly limited.

One of the emitters is shared by the holding current source 1.
connected to st. Further, the transistor Q5. Q6
The other emitter of is used as an input/output terminal of the memory cell, and is connected to a pair of representative data (or digit) lines DO, DO, respectively. Note that the driving npn transistor Q5. Q6 may be configured by two transistors each having a base and a collector connected in common.

A common connection point of load resistors R4, R5 and clamp diodes DI, D2 constituting the memory cell is connected to a word line WO, which is shown as a representative. At the center of the memory cell shown as a representative above, nX8 similar memory cells are arranged in horizontal rows, and the word line WO
connected to.

In this horizontal row, a holding current line (holding current source) 1st corresponding to the word line WO is provided, and drive transistors Q5. One of the shared emitters of Q6 is connected.

Furthermore, m memory cells similar to those described above are arranged in the vertical columns, and their input/output terminals are commonly connected to the complementary data line DO, 100. In this way, n×8×m memory cells are arranged in one row and one column to form one memory array (eight memory blocks BO to B7).

The word line WO shown as a representative is input to a word line drive circuit that receives an X address decode signal 4x.

This word line drive circuit includes Darlington type transistors Q3. Consists of Q4.

The X address decode signal X is formed by an X address decoder (not shown). An address signal supplied from an appropriate circuit device (not shown) is input to an address buffer (not shown) via an external terminal (not shown). The address buffer forms a non-inverted address signal 9 and an inverted address signal in accordance with the input address signal and transmits it to the XA IXless decoder. As a result, the X address decoder forms one word line selection signal, so one word line
F line selection is performed.

Complementary data lines Do, DO shown as a representative are connected to a constant current source 1r. Transistor Q7 as a column switch. The emitters of Q8 are connected to each other, and their on/off operation selectively connects the complementary data line DO.
, DO are made to flow a constant current generated by a constant current source 1r.

That is, transistor Q7. When QB is in the on state, a constant current of constant current 111r flows through transistor Q7. QB
, the complementary data line pair DO and DO are set to a non-selected state, and transistors Q7 . When Qfl is in the off state, the constant current is passed through the complementary data line pair DO9D''0 to set it in the selected state.The bases of these transistors Q7 and QB are
A Y address decode signal Y formed by a Y address decoder (not shown) is applied. An address signal supplied from an appropriate circuit device (not shown) is input to an address buffer (not shown) via an external terminal (not shown).

The address buffer forms a non-inverted address signal 9 and an inverted address signal according to the input address signal and transmits the generated address signal to the Y address decoder. As a result, the Y address decoder forms a data I11 selection signal, so that the pair of data lines is selected.

Note that when l block data lines are selected, the potential of the Y address decoder signal for that one block is set to low level, and the potential of the Y address decoder signal for the remaining blocks is set to high level. Also,
When the data lines of all blocks are brought into a selected state, the potential of the Y address decode signal for these blocks is set to low level. Whether one block or all blocks are selected is determined by the operation mode control signal FS as described below.

In this embodiment, when the operation mode control No. 11 FS is at a low level, one block (n pairs) of data lines is placed in a selected state. Further, if the operation mode control signal FS is at a high level, all the data lines of n pairs×8 blocks are set in a selected state. That is, nXQ bits of data are read out simultaneously.

For writing/reading of memory cells in the representative column, complementary data lines DO, DO have current switching switch transistors Q9 .
QIO is provided. These transistors Q, 9. Q
10 collector outputs have load resistances R6 and R7, respectively.
is provided, and its collector output is transmitted to the input of the sense amplifier SA. The sense amplifier SA performs the amplification operation and also performs the ECL (Emitter Couple
od Loglc; emitter coupled logic)
It forms an output signal that matches the input level of a data output sofa (not shown) consisting of. The data output cover sofa forms a read output signal to be sent from an external terminal (not shown).

The base of the current switching transistor Q9゜QIO is connected to the output voltage VA of the input circuit, which will be explained next.
VB (Vref) is applied. This evening circuit consists of differential transistors Qi3 to Q15, a constant current source IO provided at their common emitters, and the transistor Qi3 to Q15.
13. Q, the resistor R provided in each of the collectors of 14
4, R5, these resistors R4, R5, and the transistor Q,
It consists of resistors R1 and R2 in series installed between the common connection point with the collector of 15 and the ground potential point of path 2.

Said transistor Q13. The base of Q14 is a write data signal d i from a data manual buffer (not shown).
n, d In is applied. A write enable signal WE formed by a control circuit (not shown) is applied to the base of the transistor Q15-.

This evening circuit forms a read reference voltage V ref set to an intermediate level of the holding voltage of the selected memory cell during a read operation (write enable signal W1 is at a high level). Furthermore, during a write operation (the write enable signal WE is low L/bell), the 1 write circuit generates write high level and low level signals (v8) according to the complementary write data signals din and din of the data manual buffer.

VB). Such 2(+fl level In
is the transistor Q11. Q12 and a constant current source I provided at the emitter. It is transmitted to the base of QlO. The write low level signal is set lower than the low level of the holding voltage of the selected memory cell. Since such a binary level writing/reading method is well known, a detailed explanation of its operation will be omitted.

In this embodiment, two 1! during read operation! Line selection L
・Since the reference voltage Vref is also changed according to the fluctuation of the bell, the name! dynamic transistor Q1. A current switching circuit is provided which is composed of Q2 and a constant current source (1) provided at its common emitter. That is, a predetermined reference voltage ■1 is applied to the base of the differential transistor Ql of −·71), and the base of the differential transistor Q2 of
Operation mode control↓jFS is applied. The collector of the transistor Q2 is connected to the connection point between the resistors R1 and R2. That is, when the transistor Q2 is in the on state, the constant current 11 is caused to flow through the resistor Rl.

FIG. 3 shows a waveform diagram showing an example of the read operation of this embodiment.

When the operation mode control signal FS is at a low level and simultaneous reading of one bit is performed, the differential transistor Ql shown in FIG. 2 is in the on state, so the constant current 11 does not flow through the resistor R1. Further, since the write enable signal WE is at a high level, the transistor Q15 is turned on, and a constant current 0 flows through the resistors R1 and R2. As a result, the reference voltage V ref is 10X(R1+R2)
The predetermined voltage is set by . This heavy pressure is set to be at an intermediate level between the holding voltages VCI and VC2 of the selected memory cell. Note that this embodiment shows a case where the drive transistor Q5 of the memory cell is in an off state and the drive transistor Q6 is in an on state. Therefore, the holding voltage VCI at the collector of transistor Q5 goes high, and the holding voltage VC2 at the collector of transistor Q6 goes low.

Furthermore, when reading out all blocks of memory buildings (n x 8) by setting the operation mode control signal FS to a high level, the above-mentioned ff12FI! J differential transistor Q
2 enters the main state and causes a constant current 11 to flow through the resistor R1. Therefore, the voltage drop Δ■ is generated by the constant current 11 and the resistor R1. As a result, the reference voltage V ref" is lowered by the voltage ΔV. On the other hand, the selection level of the word line is lowered by ΔV by supplying the read current 1r flowing through the large number of memory cells. This lowering of the word line selection level causes the holding voltage vci of the selected memory cell to
', VC2' similarly decreases. In this example,
A reference voltage Vref" is formed to compensate for the decrease in the selection level of the word line.

As a result, the holding voltage VC1 of the selected memory cell,
The relationship between VC2 and reference voltage Vref can be kept constant. In other words, it is possible to create the same potential relationship as in the case of simultaneous reading of a small number of memory cells.

〔effect〕

(1) By changing the level of the standard output reference voltage Vref between simultaneous reading of a small number of memory cells and simultaneous reading of a large number of memory cells among the memory cells connected to the word line, Reference voltage V of the actual high-level side holding voltage applied to the selected mesori cell
An advantage of 1q is that deterioration of the margin for ref can be prevented.

(2) According to (1) above, the reference voltage V ref can be stabilized at a level between 1' and the holding voltage of the memory cell regardless of its operation mode, so the level margin can be set to the minimum necessary. can. This provides the effect of increasing the operating speed.

(3) Due to the above (11 or (2)), the operating margin can be increased, which has the effect of increasing the yield of the product.This makes it possible to mass-produce the product, so the price can be lowered accordingly. We can expect the effect of being able to do this.

(4) According to (1) or (2) above, the operation margin can be increased, thereby achieving the effect that high ta reliability of the operation can be realized.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without advancing the gist of the invention. For example, the specific circuit configuration of the memory cell can be modified to use a pnpl transistor instead of the load resistor and clamp diode. In addition, each complementary data line pair DO, DO
etc., may be provided with an additional circuit such as a bias circuit that sets a predetermined potential in a non-selected state.

Furthermore, the specific configuration of the memory array (allocation of memory blocks, number of 1! bits, etc.) can be modified as much as possible.

[Application field]

In addition to I in the computer system, the present invention provides an operation mode control signal that controls simultaneous reading of memory cells in one memory block among a plurality of memory cells connected to a word line, and simultaneous reading of memory cells across a plurality of blocks. It can be widely used as a bipolar RAM having the function of selectively performing according to the method.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing an embodiment of a bipolar RAM to which the present invention is applied, FIG. 2 is a specific circuit diagram of a main part of the embodiment of the present invention, and FIG. FIG. BO~B7...Memory block, EX...Exclusive OR circuit Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. Simultaneous reading of memory cells in one memory block among a plurality of memory cells connected to a word line and simultaneous reading of memory cells across a plurality of blocks are selectively performed according to an operation mode control signal. In a functional bipolar RAM, when simultaneously reading memory cells across multiple blocks using the above operation mode control signal,
Compared to simultaneous reading of one block of memory cells, the readout rate tP! A bipolar RAM characterized by having a level switching circuit that lowers the voltage. 2. The level switching circuit described above is composed of a circuit that divides a resistor circuit that forms a reference voltage and selectively flows a current formed by a current switching circuit that operates according to the operation mode signal to this division point. A bipolar RAM according to claim 1, characterized in that: 3. The above-mentioned bipolar RAM constitutes an index array for identifying whether or not main memory data to be processed is stored in a high-speed buffer memory provided in a computer. Bipolar RAM according to the first or second range.