JPS6046071A - Mis field effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce hot carrier effect and to suppress the irregularity of characteristics of an MIS field effect transistor by forming the low density second conductive type impurity layer on a stepwise portion between a lower channel portion of a gate oxidized film and the high density second conductive type impurity-doped layer. CONSTITUTION:A gate Si oxidized film 3 and a polycrystalline Si 4 are formed on a P type Si semiconductor substrate 1, and an impurity such as polycrystalline 4 phosphorus is doped. With a resist pattern 51 as a mask the polycrystalline Si 4 and the film 3 are etched. Arsenic ions are implanted to form N<-> type layers 5, 5'. Further, an etching is performed, and the layers 5, 5' remain on the side wall of the stepwise portion between the gate electrode 4 and the substrate 1. After the resist 51 is removed, arsenic ions are implanted to the entire surface to form N<+> type layers 6, 6', and an annealing is performed. Then, an insulating film 7 is formed, a contacting hole 8 is opened, and aluminum wirings 9 are formed. Evevtually, a protective film 10 is formed of a nitrided Si film.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a MIS field effect transistor suitable for increasing density and a method for manufacturing the same.

(Prior art) The density of MO8LSI has been increasing rapidly in recent years, and already 25
6 kilobits) DRAM 4 is at the stage of practical application.

In the future, microfabrication technology and V
CMOS FET (Metal Oxide Se
miconductorField EBect Tr
It is becoming important to miniaturize the size of the resistor. MOSFETs with source and drain formed by dart and self-line by arsenic implantation, which has been widely used in the past, have a high electric field near the drain due to the shortening of the channel length (7t, e.g. 2 μm or less). Hot carriers generated by the high electric field are injected into the dirt oxide film, deteriorating the characteristics of the MOSFET (
A hot carrier effect occurs, which indicates an upper bound on the threshold voltage TH and a decrease in transconductance 2 m. This hot carrier effect is the most serious problem in the miniaturization of MOSFETs, and in the conventional technology, there is no effective way to avoid it other than to operate with a lower power supply voltage (conventional power supply voltage 5 to 8 V) i.

However, this is not preferable from the viewpoint of compatibility with the TTL (transistor, transistor logic) level interface, which is currently widely used to lower the power supply voltage, and noise resistance.

Therefore, it is considered that with the conventional technology, miniaturization of MOSFETs is already approaching its limit.

(Object of the Invention) The present invention has been made to eliminate all of the above-mentioned drawbacks of the conventional technology, and has the purpose of eliminating all the drawbacks of the above-mentioned conventional technology. MIS with a fine structure and short channel that can reduce the intermediate carrier effect of 15FET, suppress N more accurately and reduce the dispersion of MOSFET characteristics.
The object of the present invention is to provide a type field effect transistor and a method for manufacturing the same.

(Structure of the Invention) The MIS type field effect transistor and the manufacturing method thereof of the present invention include forming a dirt insulating film on a first conductivity type semiconductor substrate or a semiconductor layer, forming a dirt electrode on the dirt insulating film, and forming a dirt electrode on the dirt insulating film. A high-concentration second conductivity type impurity doping layer is formed at a position where the semiconductor substrate or semiconductor layer is dug down in self-alignment with the dirt electrode, and the channel portion under the dirt oxide film and this high concentration second conductivity type impurity doping layer are formed. A low concentration second conductivity type impurity layer is entirely formed in the gap between the two layers.

(Example) Hereinafter, examples of the MIS type field effect transistor and its manufacturing method of the present invention will be described based on the drawings.
SFET will be explained.

FIG. 1 is a plan view of this first embodiment, and FIG. 2 is a sectional view taken along line 8-- of FIG. 1.

In both FIG. 1 and FIG. 2, 1 is a silicon semiconductor substrate, and 2 is an oxide film for isolation.

Further, 3 is a dirt oxide film, and a dirt electrode 4 is formed on this dirt oxide film 3. The drain and source are formed on the dirt electrode 4 and have an impurity concentration of lX1016 to 1x on the side wall of the step formed by the self-alignment line.
The N+ layer 6, 6' with an impurity concentration of 1.times.10@19 to I.times.10'' cm@-8 is formed at the bottom of the step with the N layer 5, 5' of the IO layer 18.

Above the step, the dirt oxide film 3 and a gate electrode 4 made of polysilicon are formed. This dirt oxide film 31 gate electrode 4 will become the source and drain N@e
, 6' are connected to the aluminum wiring 9 through contact holes 81C provided at desired locations in the insulating film 7. Finally, a protective film of 1° is formed.

Next, a method for manufacturing the above-mentioned MOSFET will be explained. Figures 3(a) to 3(f) are process explanatory diagrams of one embodiment, and in these Figures 3(a) to 3(f), the same as Figures 1 and 2 is shown. Parts will be described with the same reference numerals.

First, as shown in FIG. 3(a), a dirt silicon oxide film 3 as a dirt insulating film is formed to a thickness of 300 Å in the active region on a P-type silicon semiconductor substrate l, and (1 cf above -) electrodes are formed. 4, polysilicon 1cVDiK EX 4000A is deposited. In order to make polysilicon conductive, it is doped with an impurity such as phosphorus (I).

Next, as shown in FIG. 3(b), the polysilicon is dry-etched using the resist pattern 51 as a mask using photolithography, and then the dirt y-oxide film 3' (i-hydrofluoric acid) is etched using the polysilicon as a mask. The shape is etched as shown in FIG. 3(b).

Next, as shown in FIG. 3(C), arsenic (As) f 5
Ion implantation is performed at a dose of 10" to I x 10 tons At4 to achieve a concentration of 1 x 1016 ~
IQ 10! llll! t7n-! 'N one layer 5,5
′ is formed.

Next, as shown in FIG. 3(d), with the entire resist 51 masked, anisotropic etching is performed using a reactive ion etcher, and the silicon semiconductor substrate 1 is etched at 200 OA to 3.
000A etching. To this, L Kudart electrode 4 and P
On the side wall of the step with the type silicon semiconductor substrate 1, a layer of 5.5' of N remains under the dirt oxide film 3. If the resist 51 is removed in this state, the shape shown in FIG. 3(d) will be obtained.

Next, as shown in FIG. 3(e), 1. Using the polysilicon dirt electrode 4 as a mask, apply arsenic to the entire surface at 5×10'L5.
Ion implantation site at a dose of 2 X 10 + onsAd, concentrated K I X 10' ~I
X 1021 cm-8 (1) Form N layer 6.6'. The ion-implanted arsenic is annealed at 950° C. for 1 hour to fully electrically activate the arsenic.

Thereafter, as shown in FIG. 3(f), the insulating film 7 is
(phosphorus silica glass), contact holes 8 are fully opened at desired locations, and aluminum wiring 9 is provided. Finally, a protective film 10 is formed with a silicon nitride film, and the MOSFET
All manufacturing processes have been completed.

As explained above, in the first embodiment, the do + - in diffusion layer has an N-N structure, which suppresses electric field concentration near the drain, making it hot even in NO, 5 FETs with short dart lengths. Generation of carriers is reduced.

In the conventional structure, Mo5t"ET with an effective dart length of 2 μm
The breakdown voltage between source and drain is around 10μ, whereas the structure of this invention has an effective dart length of 1μ.
Approximately 12V can be obtained even at m, making it possible to realize a microscopic MOSFET.

In addition, the drop in threshold voltage due to the short channel is alleviated, which has the advantage of expanding margins in circuit design and manufacturing processes, and the parasitic capacitance between the gate source and gate drain is reduced due to the single layer of N on the sidewalls. However, it also has the advantage of being able to operate at high speed.

Furthermore, from a manufacturing process standpoint, the same number of masks is required compared to the conventional structure, so it can be manufactured without significantly increasing the number of steps.

The length Ls of the N single layer 5.5' is an important process parameter that controls the breakdown voltage between the source and drain (see Figure 2). Since the dose of the chision, the implantation energy, and the heat treatment in the subsequent process are determined, the length, machining time, and concentration of obtuse materials can be controlled with precision.

Therefore, the characteristics of MOSFET due to the manufacturing process.

It also has the advantage of suppressing variations.

Note that this invention can also be used for a P-channel MO8FET by using a substrate or an N-type transistor provided in the substrate and completely reversing the polarity of impurities.

Further, it is also possible to use a material other than polysilicon for the dirt electrode, such as molybdenum silicide.

(Effects of the Invention) As described above, according to the MIS type field effect transistor fabrication method of the present invention and its manufacturing method, the dirt insulating film is entirely formed on the semiconductor substrate or the semiconductor layer of the first conductivity type, and the dirt insulating film is A dirt electrode is formed entirely on top, a second conductivity type impurity doped layer is formed at a position where the semiconductor substrate or semiconductor layer is dug down in self-alignment with the dirt electrode, and this second conductivity type impurity doped layer with a high concentration is formed. Since a low concentration second conductivity type impurity layer is formed between the drain electrode and the channel portion under the dirt oxide film, electric field concentration near the drain can be suppressed.

Along with this, the generation of hot carriers is reduced even in MOSFETs with short dart lengths, and the fine MOi9F
This has the advantage that ET can be realized, and the decrease in threshold voltage caused by shortening the channel is alleviated, and the margin for circuit design and manufacturing process is expanded.

Further, there is an advantage that variations in characteristics and variations of MOSFETs in the manufacturing process can be suppressed.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a first embodiment of the MIS field effect transistor of the present invention, FIG. 2 is a sectional view at A- in FIG. 1, and FIGS. ) is the MI of this invention
1 is a diagram illustrating the entire manufacturing process of an embodiment of a method for manufacturing an S-type field effect transistor; FIG. 1... Silicon semiconductor substrate, 2... Oxide film, 3...
- Dirt oxide film, 4... Dirt electrode, 5, 5'...
N single layer, 6.6'...N layer, 7...insulating film, 8...
Contact hole, 9...aluminum wiring, 10...protective film. Patent Applicant: Oki Electric Industry Co., Ltd. No. 1 Figure 129 - Figure 3 Procedural Amendment January 18, 1948 Kazuo Wakasugi, Commissioner of the Japan Patent Office 1, Indication of Case 1982 Patent Application No. 153069 2 , Title of the invention: MISffi field effect transistor and its manufacturing method 3, Relationship with the case of the person making the amendment Patent Applicant (029) Oki Electric Industry Co., Ltd. 4, Agent 5, Date of amendment order Showa year, month, day (voluntary) ) 6. Grasping the claims and detailed description of the invention in the specification to be amended 7. Contents of the amendment 7 Contents of the amendment 1) Correct "2. Scope of claims" in the specification as shown in the attached sheet. 2) Ming #I, page 3, lines 4 and 5 [formed in. The channel length of a MOSFET with a source drain is changed to the channel length of a MOSFET with four source drains formed of
T is the channel length.'' 2. Claims (1) A dirt insulating film formed on a first conductivity type semiconductor substrate or semiconductor layer; 1. A dirt electrode formed on the dirt insulating film; A highly concentrated second conductivity type impurity dope layer formed at a position where the semiconductor substrate or the semiconductor layer is trenched, and a channel portion under the dirt oxide film and the high concentration second conductivity type impurity dope layer. An MIS type field effect transistor comprising a lightly doped layer with a second conductivity type impurity formed in a stepped portion. (2) Y-
(h) forming the entire insulating film and forming a gate electrode thereon; etching the dirt electrode leaving a predetermined area; and etching the entire dirt insulating film using the remaining dirt electrode as a mask; A step of implanting ions into the semiconductor substrate or semiconductor layer using a dirt electrode and a dirt insulating film as a mask to form a single layer of a second conductivity type impurity with a wide concentration, and a step of forming a second conductivity type impurity layer with a wide concentration; a step of performing anisotropic etching to leave the entire dopant layer of the high concentration second conductivity type impurity only under the gate insulating film; and using the gate electrode as a mask at the location where the anisotropic etching was performed. Go ahead and do Aion typing! A method for manufacturing an MIS type field effect transistor that is similar to the step of forming a layer doped with impurities of a second conductivity type. ■

Claims (2)

[Claims] (1) A dirt insulating film formed on a first conductivity type semiconductor substrate or semiconductor layer, a dirt electrode formed on the dirt insulating film, and a dirt electrode formed on the semiconductor substrate or semiconductor layer in self-alignment with the dirt electrode. A highly concentrated second conductivity type impurity doped layer formed at the dug-down position and a stepped portion between the channel portion under the dirt oxide film and the highly concentrated second conductivity type impurity doped layer. A MIS type field effect transistor comprising a lightly doped layer with a second conductivity type impurity. (2) A step of forming a dirt insulating film on the first conductivity type semiconductor substrate or semiconductor layer and forming the entire dirt electrode thereon, and etching the dirt electrode leaving a predetermined area and removing the remaining dirt electrode. etching the dirt insulating film as a mask, using the remaining dirt electrode and dirt insulating film as a mask, and performing ion implantation using the semiconductor substrate or semiconductor layer as a mask to form a highly concentrated second conductivity type impurity doped layer; High concentration 2nd
A step of anisotropically etching the conductivity type impurity doped layer to leave the highly concentrated second conductivity type impurity doped layer only under the gate insulating film, and a location where the anisotropic etching is performed. a step of performing ion implantation to form a lightly doped layer with a second conductivity type impurity, and a method of manufacturing an MIS field effect transistor made of carbon.