JPS604617B2 - three phase pulse generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a three-phase pulse generator used for stationary testing of linear synchronous motors.

A linear synchronous motor control device causes a sine wave current to flow through the armature in synchronization with the relative position of the field poles on the vehicle and the armature installed on the track.

The relative position of the field and armature is obtained by detecting markers placed along the armature on the track using onboard sensors, and is used as a three-phase synchronization signal to control the linear synchronous motor. given to the device. However, during static tests and adjustments, it is necessary to generate a simulated signal of this synchronization signal, and it is possible to generate a three-phase variable frequency pulse signal with a phase difference of 1200 and a marks base ratio of 1:1 according to the input signal. A three-phase pulse generator is required. The present invention has been made in view of these points, and an object of the present invention is to provide a three-phase pulse generator with a simple circuit configuration.

FIG. 1 shows a three-phase pulse generator according to an embodiment of the present invention.

In the figure, 1 is a variable frequency oscillator that generates an input reference pulse. 2 is a T flip-flop that generates a clock pulse with a mark-space ratio of 1:1 in synchronization with the input reference pulse; 3 is a pulse distribution circuit composed of a shift register 4 and NOR gates 6 and 7, which will be described later; 4 is an 8-bit The shift register operates in synchronization with the rising edge of a clock pulse, and the shift direction changes depending on whether the switch 5 is turned on or off.

6 and 7 are NOR gates, and 8 is a timing circuit composed of three ○ flip-flops 9 to 11. The D flip-flops 9 to 11 operate in synchronization with the rising edge of the clock pulse, but when the input to the reset terminal Ro is 0, During this time, other inputs are disabled and no output is produced.

12 is an inverter.

FIG. 2 shows an operating waveform diagram of the three-phase pulse generator of one embodiment of the invention shown in FIG.

In FIG. 2, S is the input reference pulse output from the variable frequency oscillator 1, TCX is the clock pulse output from the T flip-flop 2, and TU, TV, and TW are the output terminals A, B, and C of the shift register 4, respectively. Output pulse T
U, TV, and TW are the output pulses of the output terminals A, B, and C of the shift register after being inverted by the inverter 12, respectively;
W is the output pulse of the flip-flops 9-11.
Note that the circuit in which each of the above pulses is generated is as shown in FIG. Next, the operation will be explained.

The T flip-flop 2 generates a clock pulse TCX synchronized with the input reference pulse S.

As shown in FIG. 1, when the switch 5 is on, the shift register 4 is shifted to the right. and output pulse T
If at least one force between U and TV is r 1″, then NOR
When the output of the gate 6 becomes "0", the input to the input terminal INs of the shift register 4 becomes 0, and when the output pulses TU and TV both become 0, the output of the NOR gate 6 becomes "1".
Then, the input to the input terminal INs becomes "1", so the output pulses TU, TV, TW are equal to the clock pulse T.
In synchronization with the falling edge of CX, →TU→TV→TW- and the second
Pulses are distributed as shown in the figure. Note that when the switch 5 is off, the shift is to the left, and when at least one of the output pulses TV and TW is "1", the output of the NOR gate 7 becomes "0" and the input to the input terminal mc becomes r o ", and when the output pulses TV and TW both become 0, the output of the NOR gate 7 becomes "1" and the input of the input terminal Inc becomes "
1", the output pulses TU, TV, and TW are distributed in the order of FTW → TV → TV in synchronization with the falling edge of the clock pulse TCX. On the other hand, in the timing circuit 8, the output pulses of the D flip-flop 9 U becomes "1" in synchronization with the rising edge of the clock pulse TCX when the pulse TU is "1^", and becomes "0" in synchronization with the falling edge of the pulse TU.

Further, the output pulse V of the D flip-flop 10 becomes "1" in synchronization with the rising edge of the clock pulse TCX in the state of the pulse TV power r1", and becomes "0" in synchronization with the falling edge of the pulse TV. The output pulse W of the flip-flop 10 becomes "lr" in synchronization with the rising edge of the clock pulse TCX when the pulse TW is "1", and the output pulse W becomes "lr" when the pulse TW is "1".
It becomes "0" in synchronization with the falling of. Due to the operation of the D flip-flops 9 to 11, the frequency of the output of the timing circuit 8 matches the value obtained by dividing the output frequency of the variable frequency oscillator 1 by 1/8, and the mark space ratio is 1:1.
It becomes a three-phase pulse signal.

The phase rotation direction of this three-phase pulse signal can be easily switched by turning on and off the switch 5, and any frequency can be obtained by changing the output frequency of the variable frequency oscillator 1. As described above, the three-phase pulse generator of the present invention has the advantage that a three-phase pulse signal with a mark-space ratio of 1:1 can be obtained with a simple circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a three-phase pulse generator according to an embodiment of the present invention, and FIG. 2 is an operating waveform diagram of the three-phase pulse generator shown in FIG. In the figure, 1 is a variable frequency oscillator, 2 is a T flip-flop, 3 is a pulse distribution circuit, 4 is a shift register, and 6
, 7 are NOR gates, 8 is a timing circuit, and 9 to 11 are D flip-flops. Note that the same reference numerals in the figures indicate the same parts. Figure 1 Figure 2

Claims (1)

[Claims] 1. A variable frequency oscillator that generates an input reference pulse;
In synchronization with the above input reference pulse, the mark space ratio is 1:
A flip-flop that generates a clock pulse of NO.1, a shift register operated by the clock pulse, and a NO.1 clock pulse.
A pulse distribution circuit having an R gate, and a timing circuit having three flip-flops operated by the clock pulse, and in which the three flip-flops are sequentially reset based on the output of the pulse distribution circuit,
A three-phase pulse generator characterized in that a three-phase pulse is generated by the output of each flip-flop of the timing circuit.