JPS6046548B2 - Method for manufacturing complementary semiconductor device - Google Patents

Description

[Detailed description of the invention] The present invention relates to a method for manufacturing a complementary semiconductor device.

More specifically, the present invention relates to an improvement in a method for manufacturing a complementary semiconductor device characterized in that the formation of a well and the formation of a channel stopper within the well are performed using the same mask.
Conventionally, in manufacturing complementary semiconductor devices, separate masks were used to form a well and to form a channel stopper within the well.

Therefore, the need to form two masks naturally increases the number of steps, reduces the degree of integration due to mask alignment errors, and causes lateral diffusion of the channel stopper region during the inevitable heat treatment process in the subsequent process. It was accompanied by many drawbacks, such as a decrease in the degree of integration.
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks by using the same mask for forming a well and forming a channel stopper in the well in a method for manufacturing a complementary semiconductor device. .

The gist of this is that while using the same mask, the impurity for forming the well is, for example, phosphorus (P) in the case of N type.
) Select an impurity with a large equal diffusion coefficient, for example, 2
Ion implantation is performed with high implantation energy of about 50 KeV. (In the case of P type, the impurity is aluminum (
Al) etc. are selected. ) On the other hand, as an impurity for forming a channel stopper in the well, for example, N
In the case of a P-type, an impurity with a small diffusion coefficient such as arsenic (As) is selected, and this is ion-implanted using a low implant energy of about 140 KeV (for a P-type, an impurity such as boron (B) is ) Then, heat treatment is performed to form a deep well with impurities with a large diffusion coefficient, and at the same time form a channel cut region with a small depth with impurities with a small diffusion coefficient. There is a particular thing. In the conventional technology, separate masks were used for forming the channel stopper in the well and because the same impurity was used for forming the well and for forming the channel stopper in the well. This is because the time-consuming heat treatment is not required (the impurity dose for forming the channel stopper is larger, and the diffusion layer becomes deeper if the same heat treatment is applied).

) This method utilizes the principle that by providing a large difference in diffusion coefficient and ion implantation energy, separate diffusion layers with different depths can be obtained with the same heat treatment time. Hereinafter, with reference to the drawings, each step in a method for manufacturing a complementary semiconductor device according to an embodiment of the present invention will be explained, and the structure and unique effects of the present invention will be clarified.

A method for manufacturing a complementary semiconductor device having an N-well on a P-type silicon (Si) substrate, a P-channel transistor in the N-well, and an N-channel transistor on a P-type substrate will be described. .

Refer to FIG. 1. A P-type silicon (S1) substrate 1 is oxidized to form a silicon dioxide (SiO5) layer 2 having a thickness of about 500A, and then a layer of silicon dioxide (SiO5) having a thickness of about 1000A is formed using chemical vapor deposition. A silicon nitride (Sj3N4) layer 3 is formed.

After applying a resist film as shown in Figure 2 and removing the resist film from areas other than the areas where each unit semiconductor element (transistor) constituting a complementary semiconductor device is planned to be formed using a phosphorography method, a tetrafluoride film is applied. Using a plasma etching method using methane (CF4) and oxygen (02) as reactive gases, a silicon nitride (Si3N4) layer 3 is left only on the area where each unit semiconductor element (transistor) is to be formed, and other areas are etched. Remove this from the area.

Here, the reason why the dry etching method is used instead of the phosphoric acid (H3PO4) foil method to remove the silicon nitride (Si3N4) layer 3 is to avoid high temperature treatment. Referring to FIG. 3, a resist film 4 is applied again, and using a mask that separates the top of the well from other areas, the resist film 4 is removed from the area where the well is to be formed.

With an implantation energy of approximately 250 KeV, phosphorus (P)
) is ion-implanted. Since this implantation energy is large, phosphorus (P) is also implanted into the lower region of the silicon nitride (Si3N4) layer 3.

Furthermore, arsenic (As) is ion-implanted with an implantation energy of about 140 KeV. This driving energy
- is small, so arsenic (As) is silicon nitride (Si3
N4) Not implanted into the lower layer area. Driven only in the channel stopper area. Referring to FIG. 4, heat treatment is performed at 1200° C. for about 6 hours to form an N well 5 and a channel stopper region 6.

In this way, the N well 5 and the N+ channel stopper region 6 within the N well could be formed using the same mask. Referring to FIG. 5, the manufacturing process of the complementary semiconductor device is continued using the usual method.

That is, the P+ channel stopper region 6 of each unit semiconductor element (transistor) formed on the P-type substrate 1 is formed, and a thick silicon dioxide (SjO2) layer is formed in the region other than the region where the silicon nitride (Sl3N4) layer 3 is present. The field insulating film 8 is formed by forming phosphoric acid (H3PO4).
The silicon nitride (Sl3N4) film 3 is removed using the foil method, and the silicon dioxide (SiO2) film 2 is removed from the area not covered by the field insulating film 8 using hydrofluoric acid (HF). area with high quality silicon dioxide (Si)
A gate insulating film 9 having a thin thickness of 700 Å made of a layer of polycrystalline silicon (Si) is formed in the gate formation region.
) layer is selectively formed to form the gate 10, P type impurities are introduced into the source/drain region of the transistor formed in the N well 5 to form a P+ layer 11, and a P+ layer 11 is formed in the substrate 1. N-type impurities are introduced into the source and drain regions of the transistor to form an N+ layer 12, and the gate 1
0 is covered with an insulator 13 such as phosphosilicate glass (PSG), a source/drain gate electrode window is formed, and an electrode/wiring 14 made of aluminum (A1) or the like is selectively formed therein. Finally, a surface stabilizing film (not shown) and wire bonding (not shown) are formed to complete a complementary semiconductor device. As explained above, according to the present invention, the formation of a well and the formation of a channel stopper in the well can be performed using the same mask, reducing the number of manufacturing steps and reducing mask alignment errors and heat treatment steps. Therefore, it is possible to provide a method for manufacturing a complementary semiconductor device that can improve the degree of integration without causing irregular diffusion, etc.

The combination of well-forming impurities (with a large diffusion coefficient) and channel stopper-forming impurities (with a small diffusion coefficient), which are essential to the structure of the present invention, is important for P-type and N-type. Shown below.

AN type impurity (for P type substrate) Large diffusion coefficient Small diffusion coefficient Phosphorus (P)
Arsenic (As) Phosphorus (P) Antimony (Sb) Phosphorus (P) Bismuth (Bi) BP type impurity (for N type substrate) Large diffusion coefficient Small diffusion coefficient Aluminum (A1) Boron (B) Aluminum ( A1)
Gallium (Ga) Aluminum (A1) Indium (In) Aluminum (A1) Titanium (Ti)

[Brief explanation of drawings]

1 to 4 are cross-sectional views of a substrate showing each main step in a method for manufacturing a complementary semiconductor device according to an embodiment of the present invention. FIG. 5 is a sectional view of a substrate showing a completed state of a complementary semiconductor device according to an embodiment of the present invention. 1... Board,
2...Thin layer made of one insulator (silicon dioxide), 3...Layer made of another insulator (silicon nitride), 4...Lugist film, 5... ... Well (N well), 6 ... Channel stopper layer in well, 7 ... Channel stopper layer on substrate, 8 ... Field insulating film, 9・・・・・・
...Gate insulating film, 10...Gate, 11...
... Source and drain region of the transistor in the well, 12... Source and drain of the transistor on the substrate
Drain region, 13... Phosphorsilicate glass layer, 14
...Electrodes/wiring.

Claims (1)

[Claims] 1. A well is formed by introducing impurities of another conductivity type into a part of a semiconductor substrate of one conductivity type, and semiconductor devices having different channels are formed inside the well and in a region other than the well. In the method of manufacturing a complementary semiconductor device, (a) a thin layer made of an insulator is formed on the surface of the semiconductor substrate, and (b) a lithography method is used to remove a portion of the photoresist film. , selectively forming a layer made of another insulator on the region where each unit semiconductor element constituting the complementary semiconductor device is to be formed; (d) Using the resist film as a mask, use an ion implantation method in which the impurity having the other conductivity type and having a large diffusion coefficient is implanted with high implantation energy. and using the resist film and the layer made of the other insulating material as a mask, an ion implantation method is used to implant the impurity having the other conductivity type and a small diffusion coefficient with low implantation energy. (E)
characterized by comprising a step of performing heat treatment to form the well and a channel stopper in the well,
A method for manufacturing a complementary semiconductor device.