JPS6046590B2 - Synchronous separation circuit in television receivers - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization separation circuit in a television receiver.

Conventionally, circuits shown in FIGS. 3a and 3b are known as synchronous separation circuits.

When these circuits are configured into a monolithic integrated circuit,
I had the following problem. In both circuits, the synchronous separation transistor Q is composed of a pnp transistor. A pnp transistor formed in a monolithic integrated circuit has, for example, a well-known lateral structure in which a p-type emitter and collector region are formed simultaneously with the formation of a base region of a vertical type n-transistor, and the current amplification factor hFE is
The variation in is relatively large compared to the above-mentioned npn transistor. Therefore, the input/output transfer characteristics change. For this reason, in the above circuit, it is difficult to set a bias corresponding to the above input/output transfer characteristics, and accurate synchronous separation operation cannot be expected. The present invention was made in order to provide a synchronous separation circuit that prevents malfunctions due to variations in current amplification factors (hFE) of synchronous separation transistors.

In this invention, the base current (bias current) of the synchronous separation transistor is generated by the base current of the transistor formed under the same conditions and with a constant emitter current.

Hereinafter, the present invention will be specifically explained with reference to Examples. FIG. 1 is a circuit diagram J showing one embodiment of the present invention. This circuit connects the emitter of a synchronous separation pnp transistor Q, to which a video signal via a coupling capacitor C is applied to its base, to one voltage terminal, a power supply voltage terminal Vcc, and connects its collector to the other voltage terminal. A circuit described below is used as a base bias current circuit of the synchronous separation transistor Q, which has a load resistor i between it and a ground terminal, and whose collector receives the synchronous pulse included in the video signal. Generally, the sync separation circuit is formed in a monolithic integrated circuit that includes other circuits such as noise pulse suppression, AGC detection circuits, etc., and the bias circuit described below is also formed in this monolithic integrated circuit.

A resistor R1 is provided between the emitter of the Pnp transistor Q2 formed under the same conditions as the synchronous isolation transistor Q1, in other words, formed in the monolithic integrated circuit and the voltage terminal Vcc, and the transistor Q
The collector of No. 2 is grounded, and a forward diode D1 is provided between the base and collector.

This diode has a structure in which the base and collector of a transistor formed at the same time as the transistor O are short-circuited. Then, the collector current of the Npn transistor Q3 that forms a current mirror circuit together with the diode D1, in other words, the collector current of the Npn transistor Q3 that operates with the forward voltage of the diode D1 is used as the bias current of the synchronous separation transistor Q1. . The operation of this circuit can be explained as follows.

The power supply voltage ■Cc is, for example, about 12V, which is larger than the transistor base-emitter voltage V8llll, so even if there is some variation in this base-emitter voltage ■BIC, the emitter of the transistor Q2 and the power supply voltage terminal Vcc Since the voltage VCC-2VB0 applied across the resistor Rl, which is provided between the
: D is a constant current. Therefore, diode D1
The base current h of this transistor Q2 flowing through becomes 113≠Iday/HFE,Q2)3 (where HF
E(Q2) is the current amplification factor of transistor Q2.
The collector current of the transistor O driven by the diode D1 through which the base current 1E flows is approximately the same as the base current, and the transistor Q for separating the synchronous three
A bias current of 1 is caused to flow.

The above-mentioned synchronous separation transistor Q1 and transistor Q2
are formed under the same conditions, so their current amplification factors HFE are relatively substantially the same regardless of variations in manufacturing characteristics.

The relationship between this current amplification factor HFE and the input/output transfer characteristics of the synchronous separation transistor Q1 is as shown in FIG. ”.

As shown in this figure, as the current amplification factor decreases, the bias point a must be deepened by Δ■ as shown at a''.In other words, the synchronous separation operation cannot be performed unless the bias current is increased. In this embodiment, this variation in the current amplification factor is detected as the base current of the transistor Q2, and the signal is proportional to the reciprocal of the base current. The base bias current of the synchronous separation transistor Q1 increases as the current amplification factor decreases, or decreases as the current amplification factor increases, so that a bias current corresponding to the input/output transfer characteristics can be obtained.

Therefore, it is possible to prevent synchronization pulses from being omitted and malfunctions in which blanking pulses are extracted as synchronization pulses.

Incidentally, the bias current of the synchronous separation transistor Q1 is set in consideration of the resistor R1, the voltage ■Cc, and the current amplification factors of the transistors Ql and Q2.

As shown in the embodiments described above, the present invention is suitable for use as a synchronous separation circuit configured in a monolithic integrated circuit, but is not limited thereto. It is fine as long as it has been done.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is an input/output transfer characteristic diagram for explaining the invention, and FIGS. 3A and 3B are circuit diagrams each showing an example of the prior art. It is a diagram.

Claims (1)

[Claims] 1 A video signal is applied to the base via a coupling capacitor, the emitter is connected to one voltage terminal, and a load resistor is provided between the collector and the other voltage terminal, and this collector signal is output. a pnp-type first transistor Q_1; having a resistor between the emitter and the one voltage terminal, a forward diode between the base and the other voltage terminal, the first transistor Q_1; and a second pnp transistor Q_2 formed in the same monolithic integrated circuit as; the forward voltage of the forward diode is applied between the base and emitter, and the collector is connected to the base of the first transistor Q_1. np
An n-type third transistor Q_3 is provided, and the base bias current of the first transistor Q_1 is set by the collector current of the third transistor Q_3, thereby increasing the current amplification factor of the first transistor Q_1. A synchronous separation circuit for a television receiver, characterized in that malfunctions of synchronous separation due to variations in synchronous separation are prevented.