JPS6048059B2 - magnetic bubble storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a magnetic bubble storage device which is being put into practical use as a storage device for information processing devices and the like, and which operates by eliminating defective storage loops.

In a magnetic bubble storage device that uses a chip containing multiple storage loops, for example, a magnetic bubble storage device that uses a Meijer minor loop type chip, if there is a defect in the minor loop as a storage loop, this Information written to a loop in a defective state will be destroyed and the memory will no longer function properly.

In order to solve this drawback, Japanese Patent Application Laid-Open No. 50-6228, 5
As described in the specification of No. 1-67033, the presence or absence of defects existing in the minor loop is determined by PROM (Pro
A method is known in which PROM is stored in PROM (gramableReadOnlyMemory) and read or write operations are controlled according to the contents of the PROM, thereby avoiding the use of defective minor loops. However, the above conventional defect countermeasures have the following drawbacks. (1) A PROM is required to store the presence or absence of defects in the minor loop.

(2) If a new defective minor loop occurs, P
It is necessary to replace or rewrite the ROM.

(3) Management is complicated because it is necessary to manage the bubble chip and PROM in an integrated manner. (4) bubble,
Since the PROM must be replaced when the chip, bubble memory, or plane is replaced, an IC socket for the PROM is required, and reliability is thereby reduced.

As mentioned above, what are the conventional defect countermeasures? There have been associated drawbacks resulting in increased cost and decreased reliability of air bubble storage devices.

In order to solve the shortcomings of conventional defect countermeasures, the present invention provides information indicating the presence or absence of defects in the minor loop, that is, the good or bad state of the memory operation of the minor loop, to a specific part of the minor loop. This information is stored in the temporary storage means immediately after the power is turned on, and after that, data is written to the defective minor loop in the bubble memory chip and the defective minor A magnetic bubble storage device is provided that prohibits reading data from a loop.

Hereinafter, the present invention will be explained in detail with reference to Examples. The figure shows an example of the configuration of a magnetic bubble storage device according to the present invention.

In this embodiment, there are w minor loops with a loop length of 20 bits in the bubble memory chip, and up to two defective minor loops can be tolerated. The chip configuration of the bubble memory chip 100 is Meijia Minor.
This is a loop method, and since there are two defects 102 in the chip 100, there are two defective minor loops.

It is assumed that information at the same storage location of each minor loop 101 is information belonging to the same block, and each block is designated by block addresses 0 to 19 (BAO to 19). In the figure, each minor loop is cut and stretched at BAO for convenience. As a specific bit portion, for example, BAl6 stores information indicating whether the storage operation of the minor loop 101 is good or bad. Information "1" represented by a bubble indicated by a black circle indicates the good state of the minor loop in which that information is stored, and information "0", which is expressed as a bubble indicated by a white circle and is destroyed, indicates that the minor loop is in good condition. Indicates the defective state of the minor loop in which information is stored. In the case of the figure, 1110110111 is written in BAl6 corresponding to the good state and bad state of minor loops NO.1 to NO.1O, respectively. This information will hereinafter be referred to as good/bad information.The peripheral circuit 200 stores a block of information existing at the storage location closest to the 4-bit address register 201, the 5-bit comparator 202, and the gate 103. A 5-bit 2? block address counter 203 that indicates an address, a timing pulse generation circuit 204, a word address counter 205, a good/bad information temporary storage circuit 7 (DM) 206, a reading circuit 207,
Write circuit 208, gate drive circuit 209, AND circuit 210, 211, 212, 241, 2440R circuit 21
3,243, a NAND circuit 242, and an inverter 240.

A block address θ220, read/write designation signal 221, DM setting signal 222, and write data 223 are supplied to the peripheral circuit 200 from the outside, and the peripheral circuit 200
externally generates read data 22, read data transfer signal 225, and write data request signal 226. The DM setting signal 222 connected to the most significant bit (5th bit) of the comparator 202 has a logic value of 1 only when storing good/bad information in the bubble chip 100 to DM2O6.
The DM is set to a logical value of 0 during other normal accesses. The DM setting signal 222 is also connected to the clear input of the block address register 201 and the input of the AND circuit 210. In an access when the DM setting signal 222 is set to a logical value of 0, the block address 220 supplied from the outside is stored in the block address register 201, and the most significant bit of the input of the comparator 202 becomes a logical value of 0. There is.

Therefore, information from BAO to 15 of each minor loop 101 can be accessed. On the other hand, when accessing when the DM setting signal 222 is set to logic 1, the block
Address register 201 will be cleared and comparator 202 will be provided with a logic value of 10000.

In this case, only BAl6 in which good/bad information is stored can be accessed. Timing pulse generation circuit 20
4 is a logical 1 coincidence output 2 from the comparator 202
30 as an input, a read pulse 231 or a write pulse 232 is generated according to a read/write designation signal 221.

The read pulse 231 is generated at the timing when the information in the mager loop 106 is read by the detector 104, and the write pulse 232 specifies the timing at which the information of the write data 223 is generated by the magnetic domain writer 105. The magnetic bubble storage device of the present invention thus performs four different operations depending on the DM setting signal 222 and the read/write designation signal 221.

Next, this operation will be explained in detail. When the DM setting signal 222 has a logical value of 1 and the read/write designation signal 221 has a logical value of 0, the good/bad information is sent to B in the minor loop 101.
An operation to write to Al6 is performed.

At this time, the output of the AND circuit 241 has a logic value of 1 and generates a request signal 226 requesting transfer of write data to BAl6 of the minor loop 101. NO. is input from outside by the write data request signal 226. l~1
0 minor ● Loop 101 good ● Bad information 111011
0111 is sent, and the write circuit 208
Defective information is written to BAl6 of bubble chip 100. This operation is usually performed after the bubble memory chip or bubble memory plane has been tested. The operation when the DM setting signal 222 is set to a logic value of 1 and the read/write designation signal 221 is set to a logic value of 1 is that the good/bad information of BAl6 in the bubble chip 100 is sent to the DM2O.
There is an operation to set to 6.

That is, the BAl read by the reading circuit 207
The information of 6 is sequentially written into DM2O6 by the read pulse passed through the AND circuit 210. In the example shown, D
The minor ● loop NO. stored in BAl6 at addresses 0 to 9 of M2O6. l~10 good/bad information 1110
110111 will be written sequentially. In addition, at this time, N. The output of the AND circuit 242 has a logical value of 0, and the read data transfer signal 225 has a logical value of 0.
Instructs not to transfer read data. This operation is particularly performed immediately after power is turned on or when the chip is selectively driven. Normal access when the DM setting signal 222 is set to a logical value of 0 is made to BAO to BAl5.

During read operation, read pulse 231 and AND circuit 2
The AND circuit 212 calculates the logical product with the contents of DM2O6 obtained as the output of 44, and the read data transfer signal 225 is output to the external circuit only when read data 224 from the normal minor loop in which the storage operation is in a good state occurs. sent to. Also, during write operation, the write
D obtained as the output of the pulse 232 and the 0R circuit 243
A write data request signal 226 is generated externally by logical product with the contents of M2O6 in an AND circuit 211 so that the write data 223 is stored only in the normal minor loop. In this manner, read data 22 according to read data transfer signal 225 and write data request signal 226 is
By receiving 4 or transmitting write data 223, access is performed from the outside except for the defective minor loop. In the above explanation, the good/bad information is stored in only one block address BAl6, but it may be stored in a plurality of consecutive blocks.

For example, BAl7 stores information on the complement of BAl6, and only minor loops whose information read from BAl6 and BAl7 is (1, 0) are considered to be in good condition, and other (a) , 0), (A), 1) The minor loop where the information of (1, 1) is read is regarded as a minor loop in a bad state, and the corresponding word of DM2O6 is written for a minor loop in a good state or a bad state. It is also possible to write a logical value of 1 or O, respectively. In this case, it is possible to deal with defects in the minor loop that cause bubbles. In this case, the good/bad information in the minor loop and DM2O6
This means that the good/bad information is not in the same format. In addition, a specific bit part BAl6 that stores good/bad information
A minor loop that stores information only in minor loop NO. By providing O, the correspondence between the storage location in the minor loop and the address of the information existing at the storage location is ensured even in the event of a power failure.

That is, immediately after the power is turned on, reading operations for consecutive blocks are started, and the minor loop NO. If information indicating a good condition is read from O, the good/bad information read from other minor loops at that time is sent to DM2O6.
After writing is completed, the block address counter 203 is set to a specific value (for example, O), thereby ensuring correspondence with the address of the storage location information. Further, in the above explanation, a RAM is used for DM2O6, but a shift register can also be used.

If the number of minor loops in good condition is greater than the required number of minor loops, either the remaining minor loops in good condition are stored as good/bad information regarding them as being in bad condition, or DM Read data transfer signal 2 during normal access when setting signal 222 is set to logic 0
25 or the number of pulses of the write data request signal 226 must be limited to a prescribed number.

In the latter case, due to the new defective loop,
When the BAl6 bubble of the minor loop 101 disappears, after power is turned on, that minor loop is treated as a bad loop, and the remaining minor loops in good condition are used. As explained above, according to the present invention, RAM, which is cheaper than PROM, can be used by storing good/bad information in each minor loop block in the bubble chip that the user is not allowed to access. can do.

As a result, the aforementioned conventional drawbacks associated with the use of PROMs are overcome.
2

[Brief explanation of the drawing]

The figure is a configuration diagram showing an embodiment of a magnetic bubble storage device according to the present invention. 100 is a bubble memory chip, 101 is a minor loop, 102 is a defect, 103 is a gate, 104 is a magnetic domain detector, 105 is a magnetic domain writer, 106 is a Magier loop, 200 is a peripheral circuit, 201 is a block address・
Register, 202 is comparator, 203 is block●
Address●Counter, 204 is a timing pulse generation circuit, 205 is a word address counter, 206
207 is a read circuit, 208 is a write circuit, 209 is a gate drive circuit,
210, 211, 212, 241, 244 are AND circuits, 213, 243 are 0R circuits, 220 is a block address, 221 is a read/write designation signal, 222 is a good/good signal.
Defective information temporary storage circuit setting signal, 224 read data, 225 read data transfer signal, 223 write data, 226 write data request signal, 242 N. AN
D circuit, 240 represents an inverter.

Claims (1)

[Claims] 1. Bubble memory with major minor loop configuration
a chip and a temporary storage means, said bubble memory;
Information indicating the good/bad state of the memory operation of each minor loop is stored in a specific bit portion occupying the same portion of each minor loop of the chip, and the information indicating the good/bad state of the memory operation of each minor loop is stored in a specific bit portion occupying the same part of each minor loop of the chip, and the information indicating the good/bad state of the memory operation of each minor loop is stored, and the information indicating the good/bad state of the memory operation of each minor loop is stored when the power is turned on. Information indicating a defective state is set in the temporary storage means, and the contents of the temporary storage means prohibit writing data to and reading data from the minor loop in the defective state. Magnetic bubble storage device. 2 Except when writing information indicating a good/bad state into a specific bit part of each minor loop and when setting information indicating a good/bad state stored in the specific bit part in a temporary storage means, The magnetic bubble storage device according to claim 1, wherein access to the bit portion is prohibited. 3. Information indicating the good/bad state of the specific bit portion of the specific minor loop is used to initialize the correspondence between the storage location in the minor loop and the address of information existing at this storage location. The magnetic bubble storage device according to scope 1.