JPS6049940B2 - Electronic computer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microinstruction execution method in a microprogram type electronic computer.

In general, the execution process of an instruction word used in a program includes normal processing and exceptional processing, and the method of this exceptional processing makes a large difference in the execution speed of instructions.

For example, to explain the process of memory protection check as an example, even if the operand address is found in the computer by a predetermined address calculation, after checking whether or not this address is in the memory protection area, If memory access is performed by address, the execution speed of instructions will be slow. If processes such as memory protection checks were performed serially with normal processing in instruction word processing, the operating speed of the computer would not increase, so in recent years, such special processing has been separated from normal processing. They tend to be done in parallel. By the way, the problem here is how to stop the normal processing operation that is already in progress and move to the exception handling routine when an exceptional event occurs. This invention was made in order to deal with the above-mentioned problems. It divides a microinstruction into two parts, a preparation cycle and an execution cycle, and makes the timing pulses used in both cycles independent, so that exceptional events can be avoided. The purpose of the present invention is to provide a microinstruction execution method that solves the above-mentioned problem by suppressing the timing pulse for executing an execution cycle when a microinstruction occurs, thereby effectively inhibiting the execution of the microinstruction at this time. It is something to do. Next, the present invention will be explained in detail with reference to the drawings.

1 and 2 are diagrams for explaining the present invention, respectively. FIG. 1 is a diagram showing the execution process of a microinstruction and the generation status of a timing pulse corresponding thereto, and FIG. FIG. 3 is a diagram showing the relationship between execution suspension and timing pulses when an exceptional event occurs during the execution process of an instruction. In these figures, 1 is the first microinstruction, 2 is the second microinstruction, 3 is the third microinstruction, 4 is the fourth microinstruction, and 5 is the timing T for the preparation cycle.

, 6 is the timing Ti for the preparation cycle, 7 is the timing T2 for the execution cycle, and 8 is the timing T for the execution cycle.
3. A represents the preparation cycle portion of the first half of the microinstruction, and B represents the execution cycle portion of the second half of the microinstruction. As shown in Figure 1,
The execution format of each microinstruction is divided into a preparation cycle A and an execution cycle B.

The execution cycle of one microinstruction and the preparation cycle of the next microinstruction are overlapped. The timing for controlling the execution operation of each cycle is T for the preparation cycle. and T1, and T2 and T3 are provided independently for execution cycles. Normally, when a microinstruction is executed, a decoder for the microinstruction and operation data are prepared in a preparation cycle, and an operation and the result of the operation are stored in an execution cycle. When the previous microinstruction enters the execute cycle, the next microinstruction enters the prepare cycle. Now, the instruction execution method according to the present invention will be explained using the example of the memory protection check mentioned above.

It is assumed that calculation of the operand address is completed by the first microinstruction, and memory access is performed by the second microinstruction. It is assumed that the first micro-instruction instructs a memory protection check, and the result of the check is known before the execution cycle of the second micro-instruction. If it is found as a result of the memory protection check that the location is not an access-prohibited location, the execution of microinstructions proceeds from the first microinstruction to the second and third microinstructions, as shown in FIG. However, if an exceptional event occurs in which the memory protection check reveals that access is prohibited, the second and third
The supply of timing pulses T2 and T3 for each execution cycle B (shaded area) of the microinstruction is suppressed, leaving the same state as before without executing anything. The reason why the execution cycle of the third microinstruction is also inhibited is due to the exception that access is prohibited as a result of the memory protection check during this time. This is because the first microinstruction (corresponding to the position of the fourth microinstruction in terms of generation time) for processing the occurrence of the error is read out and the operation is entered into the exception handling routine. The instruction execution method according to the present invention described above can be realized by the circuit shown in FIGS. 3 and 3, which will be explained below.

FIG. 3 is a block diagram showing the circuit configuration of essential parts necessary for carrying out the present invention. In FIG. 3, reference numeral 9 indicates an incoming line for an exceptional event occurrence signal, 10 indicates an OR gate, 11 indicates a flip-flop, 12 indicates an oscillator, 13 indicates a phase adjustment circuit, and 14 indicates a timing distributor. The oscillation output generated by the oscillator 12 undergoes phase adjustment in the phase adjustment circuit 13, and
timing signal T.

to T3 and are sent from the timing distributor 14 to each execution unit (not shown). On the other hand, the occurrence of an exception factor is detected by the exception event occurrence signal incoming line 9 and sent to the OR circuit 1.
Set the flip-flop 11 through 0. Then, by ANDing the output of the flip-flop 11 and the timing signals T2 and T3 of the timing distributor 14, it is possible to suppress the transmission of the timing signals T2 and T3. Thus, when an exceptional event occurs, the T2 and T3 timing signals are inhibited. In this way, while the execution of the second and third microinstructions is inhibited, the first microinstruction of the exception handling routine is read out and the exception handling is executed, as described above. As is clear from the detailed description of the present invention described above, according to the present invention, execution of a microinstruction can be stopped by simply suppressing the generation of timing at the source of timing signal distribution. This means that the abort circuit has been greatly simplified. This also solves the problem of overlapping normal processing and exception processing, which leads to improved performance as a computer.It can be applied not only to the example of memory protection checking but also to various other types of exception processing. It is possible to obtain effects such as easy operation.

[Brief explanation of the drawing]

1 and 2 are diagrams necessary for explaining the present invention, respectively, and FIG. 1 is a diagram showing the execution process of a microinstruction and the generation situation of a timing pulse corresponding thereto, and FIG.
The figure shows the relationship between execution stop and timing pulses when an exception occurs during the execution process of a microinstruction. FIG. 3 is a block diagram showing the circuit configuration of essential parts necessary for carrying out the present invention. In the figure, 1 to 4 are microinstructions, 5 and 6 are preparation cycle timings, 7 and 8 are execution cycle timings, A is the preparation cycle portion of the microinstruction, B is the execution cycle portion, and 9 is an exception event occurrence signal. 10 is an incoming line, 10 is an OR circuit, 11 is a flip-flop, 12 is an oscillator, 13 is an in-phase adjustment circuit, and 14 is a timing distributor.

Claims (1)

[Claims] 1. In an electronic computer using a microprogram control system in which a microinstruction consists of a preparation cycle part and an execution cycle part, and the execution cycle of a microinstruction and the preparation cycle of the next microinstruction overlap, An electronic device characterized in that an independent timing is prepared for the execution cycle, and when an exception event occurs, execution is inhibited by inhibiting the timing of the execution cycle of subsequent microinstructions, and the operation is entered into the exception handling routine. calculator.