JPS6051271B2 - Stacked CMOS inverter device - Google Patents

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a stacked CMOS inverter device.

[Technical background of the invention]

2. Description of the Related Art Conventionally, a structure shown in FIG. 1 has been known as a stacked CMOS inverter device using a silicon substrate.

That is, 1 in the figure is a p-type silicon substrate, and this substrate 1
A field oxide film 2 for element isolation is provided on the surface. In an island-shaped substrate 1 region separated by a field oxide film 2, n1 source and drain regions 3 and 4 electrically isolated from each other are provided. A gate oxide film 5 is formed on the substrate 1 between these source and drain regions 3 and 4.
A gate electrode 6 is provided via the gate electrode. The entire surface including this gate electrode 6 is covered with a thin carbon film that functions as a gate insulating film.
VD-SIO. Membrane 7 is coated and CVD-SiO.
A through hole 8 is provided in a portion of the film 7 corresponding to the source region 3 . Also, CVD-SiO around the gate electrode 6. A polycrystalline silicon film 9 is formed on the film 7.
, and a portion of the polycrystalline silicon film 9 is in contact with the source region 3 of the substrate 1 via the through hole 8 . This polycrystalline silicon film 9 is provided with p' source and drain regions 10 and 11 electrically isolated from each other in a portion of the polycrystalline silicon film 9 that faces the gate electrode 6. The p1 source region 10 provided in the polycrystalline silicon film 9 is in contact with the n1 source region 3 of the substrate 1 via the through hole 8 of the CVD-SiO2 film 7. Furthermore, CV is formed on the entire surface including the polycrystalline silicon film 9.
D-SIO. An interlayer insulating film 12 such as the like is coated. Then, on this interlayer insulating film 12, the insulating film 12 and the CVD-SiO are formed. Contact hole 13 penetrating membrane 7
A wiring (
A power supply electrode) 14 is provided. An Al wiring (power supply electrode) 15 is provided on the insulating film 12 and connected to the p1 drain region 11 via a contact hole 13 penetrating the insulating film 12. Furthermore, an N wiring (signal output electrode) 16 is provided on the insulating film 12 and connected to the p+ source region 10 via a contact hole 13 penetrating the insulating film 12. In this CMOS inverter device, an n-channel MOS transistor is formed on the substrate 1 side, a p-channel MOS transistor is formed on the laminated polycrystalline silicon film 9, and the gate electrode 6 is formed on the n-channel MOS transistor.
It serves as a common electrode for channel and p-channel MOS transistors. The equivalent circuit of the inverter device shown in FIG. 1 described above is shown in FIG. 2.

Here, Q1 is a p-channel MOS transistor, Q2 is an n-channel MOS transistor, G is a gate terminal, and O
is an output signal terminal, and ■DD and ■S$ are power supply terminals, respectively. Normally, the power terminal ■Ss is at ground potential, and ■DD is 1~
Set it to about 5V and operate the inverter. [Problems with the Background Art] In the CMOS inverter device described above, as shown in FIG. However, the source region 3 of the n-channel MOS transistor and the source region 10 of the p-channel MOS transistor are in direct contact through the through hole 8, and a Pn junction is formed between them, as shown in FIG. Like parasitic diode D1
is formed between n-channel MOS transistor Q2 and output signal terminal 0.

When such a parasitic diode D1 exists, the output voltage outputted to the output signal terminal 0 has a response characteristic with respect to the input voltage inputted to the gate terminal G as shown in FIG. That is, even if the input voltage to the gate terminal G increases and the p-channel MOS transistor Q1 turns off and the n-channel MOS transistor Q2 turns on, the output voltage does not reach the V$$ level and the parasitic diode D
The potential difference at the Pn junction of 1 is biased by 8 times. Therefore, the inverter device shown in FIG. 1 has the disadvantage that the output signal amplitude becomes correspondingly smaller and it becomes difficult to distinguish the signal level, that is, to distinguish between ゛゜0゛ or -“1゛.Usually, the Pn junction Since the contact potential is about 0.7 V, it becomes a big problem in terms of signal level discrimination, especially when the power supply potential used is lowered.The problem mentioned above is that the p-channel M
The same problem occurs in a CMOS inverter device in which an OS transistor is formed and an n-channel MOS transistor is formed in a polycrystalline silicon film.

An equivalent circuit of the inverter device in this case is shown in FIG. 4, and a response characteristic of the output signal voltage to the input signal voltage at that time is shown in FIG. In FIG. 4, Q''1 is a p-channel MOS transistor, Q''2 is an n-channel MOS transistor, and D2 is a parasitic diode. [Object of the Invention] The present invention was made in view of the above circumstances, and by eliminating the parasitic diode formed between the n-channel MOS transistor and the output signal terminal, it is possible to obtain an output signal with a sufficiently large amplitude. The present invention aims to provide a stacked CMOS inverter device.

[Summary of the invention]

The present invention provides a defective layer at the interface of the semiconductor film portion stacked on the semiconductor substrate that contacts the source region of the MOS transistor provided on the semiconductor substrate side, thereby forming an n-channel MOS transistor in a stacked state. A stacked CMOS that suppresses the rectification of the Pn junction formed between the source regions of p-channel MOS transistors, has a sufficiently large signal amplitude, has a good signal level, and can operate at high speed.
The main point is to obtain an inverter device.

[Embodiments of the invention]

Next, an embodiment of the present invention will be described in detail with reference to a manufacturing method shown in FIG. 6a-1.

(1) First, a p-type silicon substrate 101 was selectively oxidized to form a field oxide film 102 for isolating the substrate 101 (as shown in FIG. 6a).

Next, a thermal oxidation treatment is performed in an oxygen atmosphere at 1000°C to grow an oxide film 103 with a thickness of, for example, 250A on the island-shaped substrate 101 region (device region) separated by the field oxide film 102, and further on the entire surface. For example, after depositing a polycrystalline silicon film with a thickness of 3500 Å using the CVD method, a gate electrode 104 made of polycrystalline silicon was selectively formed on the oxide film 103 by patterning using a photoetching technique (as shown in FIG. 6b). ). (Ii) Next, using the gate electrode 104 and field oxide film 102 as a mask,
Type impurities, such as arsenic, were ion-implanted into the substrate 101 through the oxide film 103 under conditions of an acceleration voltage of 50 ke and a dose of 1.times.10@15 /Clt (as shown in FIG. 6c). Subsequently, after performing heat treatment to activate the arsenic ion implantation layer and forming n+ type source and drain regions 105 and 106,
The oxide film 103 was selectively etched using the gate electrode 104 and the like as a mask to form a gate oxide film 107 (as shown in FIG. 6d).

(Iiii) Next, the entire surface is coated with a thickness of, for example, 250 Å, which acts as a gate oxide film of the p-channel MOS transistor.
(7) After depositing the CVD-SiO2 thin film 108, a through hole 109 was formed in a portion of the CVD-SiO2 thin film 108 facing a part of the n+ type source region 105 by photoetching (as shown in FIG. 6e).

Next, the entire surface is coated with a thickness of, for example, 3000A by CVD method.
After depositing a polycrystalline silicon film, it is patterned using a photoetching technique to form a polycrystalline silicon film pattern 110 as a semiconductor film in a region on the CCD-SiO2 thin film 108 including the through hole 109 and the gate electrode 104. (as shown in Figure 6f). (1v) Then,
After forming a resist pattern 111 on the polycrystalline silicon film pattern 110 corresponding to the gate electrode 104, using the resist pattern 111 as a mask, a p-type impurity, for example, boron, is added at an acceleration voltage of 40ke and a dose of 1X1015.
Ions were implanted into the polycrystalline silicon film pattern 110 under the condition of /CIL (as shown in FIG. 6g).

Note that prior to boron implantation, an n-type impurity such as arsenic is ion-implanted into the polycrystalline silicon film pattern 110, which will become the channel region, for threshold control, or an energy beam such as a laser beam is irradiated to form the polycrystalline silicon film. The pattern 110 may be made into a single crystal or its crystallinity may be improved. (V) Next, after removing the resist pattern 111, heat treatment was performed.

At this time, the boron ion implantation layer was activated and p+ type source and drain regions 112 and 113 were formed in the polycrystalline silicon film pattern 110. Continuously, a region other than the polycrystalline silicon film pattern 110 near the through hole 109 is covered with a resist pattern 114, and using the resist pattern 114 as a mask, for example, phosphorus is applied at an accelerating voltage of 15
Ion implantation was performed at a 0 keV1 dose of 5×1α5/d. At this time, the substrate 101 is inserted through the through hole 109.
source region 105 and polycrystalline silicon film pattern 110
Damage was caused to the interface of the portion, and a defective layer 115 was formed (as shown in FIG. 6h). Subsequently, after removing the resist pattern 114, the entire surface is coated with a film having a thickness of, for example, 8000A (7).
Deposit CVD-SiO2 film 116 and contact hole 1
17... After opening a hole, an Al film is deposited and patterned to form an Al wiring (power supply electrode) connected to the n+ type drain region 106 via a contact hole 117.
118, AI wiring (power supply electrode) 119 connected to the p+ type drain region 113 via the contact hole 117;
and p+ type source region 112 and contact hole 117
A layered CMOS inverter device was manufactured by forming wiring (signal output electrode) 120 connected to the wafer through the wafer (as shown in FIG. 6i). As shown in FIG. 6, the stacked inverter device of the present invention has n+ type source and drain regions 105 and 106 electrically isolated from each other in an island region of a p type silicon substrate 101. A gate electrode 104 is formed on a gate oxide film 107 on a region of the substrate 101 including at least a portion sandwiched between source and drain regions 105 and 106.
C on the region including the gate electrode 104.
A polycrystalline silicon film pattern 110 is provided through the VD-SiO2 thin film 108, and a p+ type source is provided on the polycrystalline silicon film pattern 110, electrically isolated from each other at a portion of the pattern 110 facing the gate electrode 104. , drain regions 112 and 113 are provided, and the substrate 1
01 type source region 105 and the p + type source region 113 of the polycrystalline silicon film pattern 110 are formed by CVD-SlO.
2 through the through hole 109 of the thin film 108.
The structure is such that they are in contact through 5.

In other words, the source region 105 of the n-channel MOS transistor formed on the p-type silicon substrate 101 and the substrate 1
Polycrystalline silicon film pattern 110 laminated on 01.
Since it is in contact with the p+ type source region 112 through the defect layer 115, the rectification effect of the parasitic diode generated between the source regions 105 and 112 can be suppressed. Therefore, when the inverter device is operated by inputting a voltage to the common gate electrode 104, the signal output from the signal output electrode 120 is as follows. . , ■S, can be output with full swing, and signal level discrimination can be significantly improved. In this embodiment, micro defects are generated in the defective layer 115 by heat treatment in the N metallization process, but if this is insufficient, another appropriate heat treatment may be performed. . In the above embodiment, an n-channel MOS transistor was formed on the substrate, and a p-channel MOS transistor was formed on the polycrystalline silicon film pattern (semiconductor film) laminated on the substrate.
A CMOS inverter device having similar effects can be realized by forming a channel MOS transistor and an n-channel MOS transistor in a semiconductor film, respectively.

In the above embodiment, the gate electrode is formed of polycrystalline silicon, but the gate electrode is not limited to this. For example, MOIPt. ．． w. ．． P
It may be formed of a metal such as d or a silicide thereof.

In the above embodiment, the defective layer was formed by ion implantation of phosphorus, but the defective layer may be formed by ion implantation of other impurities, such as arsenic or argon.

Furthermore, the stacked CMOS inverter device according to the present invention is limited to a structure using a silicon substrate as in the above embodiment;
A structure using a substrate also has similar effects.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to obtain a sufficiently large output signal with good signal level discrimination, and to provide a stacked CMOS inverter device capable of high-speed operation.

[Brief explanation of drawings]

Figure 1 is a sectional view of a conventional stacked CMOS inverter device, Figure 2 is an equivalent circuit diagram of the inverter device in Figure 1, and Figure 3 is an equivalent circuit diagram of the inverter device in Figure 1.
The figure is a characteristic diagram showing the relationship between the input signal voltage and the output signal voltage of the inverter device shown in FIG. 1, FIG. 4 is an equivalent circuit diagram of another conventional stacked CMOS inverter device, and FIG. A characteristic diagram showing the relationship between the input signal voltage and the output signal voltage of the inverter device, and FIG. 6 a-1 is a sectional view showing the manufacturing process for obtaining a stacked CMOS inverter device which is an embodiment of the present invention. . 101...p-type silicon substrate, 102...
・Field oxide film, 104...gate electrode,
105...Chug-shaped source area, 106...
・N+ type drain region, 107...Gate oxide film, 108...CVD-SlO2 thin film, 109
...Through hole, 110...Polycrystalline silicon film pattern (semiconductor film), 112...p+
type source region, 113... p+ type drain region, 115... defect layer, 118, 119, 120...
...N wiring.

Claims (1)

[Claims] 1. At least includes a semiconductor substrate of a first conductivity type, source and drain regions of a second conductivity type provided electrically isolated from each other on the surface of this substrate, and a portion sandwiched between these source and drain regions. a gate electrode provided on a region with a first insulating film interposed therebetween; a semiconductor film laminated on a region including the gate electrode with a second insulating film interposed therebetween; and a gate electrode provided on this semiconductor film. In the stacked CMOS inverter device, the source region of the semiconductor substrate and the source region of the semiconductor film are electrically separated from each other by a semiconductor film portion facing each other. A stacked CMOS inverter device characterized in that a defective layer is provided in a semiconductor film portion of a contacting interface.