JPS6051287B2 - Exclusive OR circuit device using Josephson elements - Google Patents
Exclusive OR circuit device using Josephson elementsInfo
- Publication number
- JPS6051287B2 JPS6051287B2 JP55091371A JP9137180A JPS6051287B2 JP S6051287 B2 JPS6051287 B2 JP S6051287B2 JP 55091371 A JP55091371 A JP 55091371A JP 9137180 A JP9137180 A JP 9137180A JP S6051287 B2 JPS6051287 B2 JP S6051287B2
- Authority
- JP
- Japan
- Prior art keywords
- josephson
- counter electrode
- signal
- current
- junction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/195—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、極めて簡単な構造で排他的論理和動作を行
えるようにしたジョセフソン素子利用の論理回路装置に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic circuit device using a Josephson element that is capable of performing an exclusive OR operation with an extremely simple structure.
ジョセフソン接合は周知のように、超伝導電子のトン
ネリングが可能な程度に薄い絶縁薄膜を介して2つの超
伝導体を接触させたものであり、第1図をに示す如き電
圧V、電流I特性を持つ。As is well known, a Josephson junction is a junction in which two superconductors are brought into contact via an insulating thin film thin enough to allow tunneling of superconducting electrons, and the voltage V and current I are as shown in Figure 1. have characteristics.
即ちこの接合の両端の電圧Vが0でも電流が流れ(詳し
くは、このとき流れる超伝導電流isはi。sin(θ
。−θ、)で表わされるから、両超伝導体の位相差θ、
、θ。が零でなければ)、そして外部電極よりこの接合
に電流を流してそれを臨界値Ic以上にすると上記の超
伝導電流isでは不足するので常伝導電流も流れること
になり、接合には電 圧が生じる。この臨界値Icは磁
場によつて増減する。そこで第1図aに示すようにジョ
セフソン接合Jに図示しない定電流源よりバイアス電流
IBを供給し、信号線に信号電流IHを流して該電流が
生じる磁場をジョセフソン接合Jに加える状態を考える
に、IH■0、1B<1cてあれば第1図 をに示され
るように接合両端に現われる電圧Vは 0であるが、信
号電流IHを流して磁界を作用させ、IcをI’cに下
げると1B>1’cとなり、動作点は点線で示す負荷直
線に沿つて点Pへ飛び、接合Jには電圧が発生する。I
H■0従つてIcは不変にしてIBf!−1’Bに増大
させても結果は同様で、動作点はP’となり、電圧が発
生する。以上がジョセフソン論理ゲートの動作の概要で
ある。 通常のジョセフソン論理ゲートではジョセフソ
ン接合Jの回路と信号電流IHの回路とは分離独立して
いるが、この形式では多層構造となり(ジ ョセフソン
接合が3層構造であり、これに絶縁層を介して信号線を
取付けると5層構造となり、こJれに更に磁界を接合J
に有効に与えるようにするグランドプレーンと絶縁層が
加つて7層構造となる)、断線発生等、製造上難点があ
る。In other words, even if the voltage V across this junction is 0, a current flows (more specifically, the superconducting current is flowing at this time is i.sin(θ
. −θ, ), so the phase difference between both superconductors θ,
, θ. If current is passed through this junction from the external electrode to make it above the critical value Ic, the superconducting current is insufficient, so a normal current will also flow, and a voltage will be applied to the junction. occurs. This critical value Ic increases or decreases depending on the magnetic field. Therefore, as shown in Fig. 1a, a bias current IB is supplied to the Josephson junction J from a constant current source (not shown), a signal current IH is passed through the signal line, and the magnetic field generated by the current is applied to the Josephson junction J. Thinking about it, if IH■0,1B<1c, the voltage V appearing across the junction is 0, as shown in Figure 1, but when a signal current IH is applied and a magnetic field is applied, Ic becomes I'c. When the voltage is lowered to 1B>1'c, the operating point jumps to point P along the load straight line indicated by the dotted line, and a voltage is generated at junction J. I
H■0 Therefore, Ic remains unchanged and IBf! Even if it is increased to -1'B, the result is the same, the operating point becomes P', and a voltage is generated. The above is an overview of the operation of Josephson logic gates. In a normal Josephson logic gate, the Josephson junction J circuit and the signal current IH circuit are separated and independent, but in this type, they have a multilayer structure (the Josephson junction has a three-layer structure, and an insulating layer is added to this). When the signal line is attached through the
(Adding a ground plane and an insulating layer to effectively provide a 7-layer structure), there are manufacturing difficulties, such as the occurrence of wire breakage.
そこで本出願人は先にジョセフソン接合の一方の超伝導
体(対向電極)に信号線を直結し、(対向電極それ自5
体を信号線とし)かつ該対向電極をグランドプレーンヘ
直結した(直結しないでこの部分に抵抗が入ると、信号
電流による電圧降下が該抵抗に発生し、これは出力端電
位を変えて信号電流が出力回路に漏れたことになる)対
向電極直結型ジョセフソン論理ゲートを案出した。これ
は特願昭55−20214に説明してあるが、その概要
を第1図C,dで説明すると10はグランドプレーン、
12,14,16がジョセフソン接合を構成する超伝導
体およびトンネリング可能な薄層、18は絶縁層である
。対向電極直結型のジョセフソン論理ゲートでは対向電
極16を延長してその延長部16aから信号電流1Hを
流し、他端16bはグランドプレーン10へ落とし、出
力電圧は基部電極12から取出す。従つて等価回路は第
1図aの如くなる。この型のジョセフソン論理ゲートは
信号線部の2層を節約てき、断線発生阻止、歩留向上に
有効てある。また信号電流回路と出力電流回路とは接合
Jて分離されており、入力電流が出力回路へ漏れるとい
うような問題もない。ところで周知のように論理ゲート
には論理積、論理和、排他的論理和(以下EXORとい
う)など種々あり、これらは半導体素子で構成されるこ
とが多い。Therefore, the applicant first directly connected a signal line to one superconductor (counter electrode) of the Josephson junction, and
(the body is used as a signal line), and the counter electrode is directly connected to the ground plane (if a resistor is inserted in this part without being directly connected, a voltage drop due to the signal current will occur in the resistor, and this will change the output terminal potential and reduce the signal current.) He devised a Josephson logic gate with a direct connection to the counter electrode. This is explained in Japanese Patent Application No. 55-20214, and the outline is explained in Fig. 1C and d. 10 is a ground plane,
12, 14, and 16 are superconductor and tunnelable thin layers constituting a Josephson junction, and 18 is an insulating layer. In the Josephson logic gate of the counter electrode direct connection type, the counter electrode 16 is extended and a signal current 1H flows through the extended portion 16a, the other end 16b is dropped to the ground plane 10, and the output voltage is taken out from the base electrode 12. Therefore, the equivalent circuit is as shown in FIG. 1a. This type of Josephson logic gate saves two layers in the signal line section, and is effective in preventing disconnections and improving yield. Furthermore, the signal current circuit and the output current circuit are separated by a junction J, so there is no problem of input current leaking to the output circuit. By the way, as is well known, there are various types of logic gates such as AND, OR, and exclusive OR (hereinafter referred to as EXOR), and these gates are often constructed from semiconductor elements.
勿論ジョセフソン素子で作ることも可能であるが、ジョ
セフソン素子利用のEXORは余り例を見ない。EXO
Rは論理信号てはA4Blこれは(A−B) (A+
B)または(A+B)+(A−B)と展開できるのでナ
ンド、アンド、オーア各回路の組合せまたはアンドとノ
アの組合せで構成できるが、これでは素子が相当に複雑
になる。それ故本発明は可及的に簡単な構造でEXOR
論理を実行できるジョセフソン素子利用の論理回路!装
置を提供しようとするものであり、その特徴とする所は
グランドプレーン上に絶縁層を介してT字型の基部電極
を設け、該T字型の水平腕部の上を延び信号線を兼ねる
対向電極を設け、そして該水平腕部の両端において該対
向電極との間にジヨ5セフソン接合を形成させ、これら
のジョセフソン接合の中間における該対向電極の前記T
字型の垂直脚部とは逆側の突出部をグランドプレーンへ
接続し、該基部電極の垂直脚部をバイアス電流入力およ
び信号出力端、前記対向電極の両端をそれぞ4れ信号入
力端としてなる点である。Of course, it is also possible to use a Josephson element, but there are very few examples of EXORs using Josephson elements. EXO
R is a logic signal. A4Bl This is (A-B) (A+
Since it can be expanded as B) or (A+B)+(A-B), it can be constructed by a combination of NAND, AND, and OR circuits, or a combination of AND and NOR circuits, but this would make the element considerably complicated. Therefore, the present invention provides EXOR with the simplest possible structure.
A logic circuit using Josephson elements that can execute logic! The device is characterized by a T-shaped base electrode provided on the ground plane via an insulating layer, which extends over the horizontal arm of the T-shape and also serves as a signal line. A counter electrode is provided, and a Josephson junction is formed between the counter electrode and the counter electrode at both ends of the horizontal arm, and the T of the counter electrode is formed between the Josephson junctions.
The protrusion on the opposite side to the vertical leg of the shape is connected to the ground plane, the vertical leg of the base electrode is used as a bias current input and signal output terminal, and both ends of the counter electrode are used as signal input terminals. This is the point.
第2図にその実施例を示す。第2図でaは平面図、bは
側面図を示し、aのX−X線部はbでは断面にしてある
。An example of this is shown in FIG. In FIG. 2, a shows a plan view, b shows a side view, and the section taken along the line X--X in a is shown in cross section in b.
10はグランドプレーン、18は絶縁層、12は基部電
極である。10 is a ground plane, 18 is an insulating layer, and 12 is a base electrode.
基部電極12は本例ではT字型をしており、その水平腕
部12a上に信号線を兼ねる対向電極16が左、右に延
びている。対向電極16は水平腕部12aの両端におい
て基部電極とジョセフソン接合を形成しており、14a
,14bがその絶縁薄膜である。対向電極の両端延長部
16a,16bは信号電流の入力端となり、また対向電
極16の突出部16cはグランドプレーン10フと接続
される。T字型の基部電極の垂直脚12bはバイアス電
流の入力端および信号出力端となる。これは第1図と対
比すれば明らかなように、この第1図の対向電極直結型
ジョセフソン素子を2個併設した構造をなす。この装置
の動作を説明するとバイアス電流1Bは基部電極12の
垂直脚部12b、同水平腕部12a1絶縁薄膜14a,
14b、対向電極16、突出部16c1グランドプレー
ン10の経路で流れ、また信号電流1H1,IH2は対
向電極の延長部16a,16b1対向電極16、および
突出部16C1グランドプレーンの経路で流れる。The base electrode 12 is T-shaped in this example, and a counter electrode 16 that also serves as a signal line extends to the left and right on the horizontal arm portion 12a. The counter electrode 16 forms a Josephson junction with the base electrode at both ends of the horizontal arm 12a, and the counter electrode 16 forms a Josephson junction with the base electrode at both ends of the horizontal arm 12a.
, 14b is the insulating thin film. The extensions 16a and 16b at both ends of the counter electrode serve as input ends for a signal current, and the protrusion 16c of the counter electrode 16 is connected to the ground plane 10. The vertical leg 12b of the T-shaped base electrode serves as a bias current input end and a signal output end. As is clear from comparison with FIG. 1, this has a structure in which two Josephson elements of the opposite electrode directly connected type shown in FIG. 1 are provided side by side. To explain the operation of this device, the bias current 1B is applied to the vertical leg portion 12b of the base electrode 12, the horizontal arm portion 12a1, the insulating thin film 14a,
14b, the counter electrode 16, the protrusion 16c1 and the ground plane 10, and the signal currents 1H1 and IH2 flow in the extensions 16a and 16b1 of the counter electrode, the counter electrode 16, and the protrusion 16C1 through the ground plane.
上記バイアス電流1Bの値は、信号電流1H1,IH2
が共にOのとき、ジョセフソン接合J,,J2がいずれ
も無電圧状態であるように選ばれる。これに信号電流1
H1またはIH2が流れると該電流が生じる磁界により
磁界により接合の臨界電流値は下り、h〉IOとなつて
接合Jl,J2は電圧状態となる。次に信号電流1H1
,IH2が共に流れると対向電極16におけるこれらの
電流の方向は逆であるから該電流が作る磁束は打消し合
い、信号電流1H1,1H2がいずれも0である状態と
同じになつて接合Jl,J2は無電圧状態になる。今信
号電流が流れる状態を1、流れない状態を01接合が電
圧状態であるのを1、無電圧状態てあるのをOとすると
上記は00または11で0,01または10で1となり
、EXOR論理動作が行なわれたことになる。なおこの
場合の臨界電流1cに対する信号電流の働きは第1図の
場合とは若干異なり、所詐PCSQUIDのそれと似て
いる。以上の説明から明らかなように本発明によれば極
めて簡単な構造のジョセフソン利用のEXORゲートが
得られる。The value of the bias current 1B is the signal current 1H1, IH2
are both O, Josephson junctions J, , J2 are both chosen to be in a voltage-free state. This has a signal current of 1
When H1 or IH2 flows, the critical current value of the junction decreases due to the magnetic field generated by the current, h>IO, and the junctions Jl and J2 enter a voltage state. Next, signal current 1H1
, IH2 flow together, the directions of these currents in the counter electrode 16 are opposite, so the magnetic fluxes created by these currents cancel each other out, and the state is the same as when the signal currents 1H1 and 1H2 are both 0, and the junction Jl, J2 becomes a no-voltage state. Now, if the state where the signal current flows is 1, the state where it does not flow is 01, the voltage state of the junction is 1, and the state where there is no voltage is O, then the above is 00 or 11, 01 or 10 is 1, and EXOR A logical operation has been performed. Note that the function of the signal current with respect to the critical current 1c in this case is slightly different from that in the case of FIG. 1, and is similar to that of the fraudulent PCSQUID. As is clear from the above description, according to the present invention, an EXOR gate utilizing Josephson can be obtained with an extremely simple structure.
なおこの装置では最初に信号を与え、その後バイアス電
流を流して出力を読むようにするのがよい。これは、特
に信号電流1H1,IH2を共に流す場合、両者に時間
差があると一方の信号電流が流れたとき電圧状態となつ
てしまい、これは保持されてしまつて他方の信号電流が
流れても解除されない(解除はリセットで行なわれる)
からである。Note that with this device, it is preferable to first apply a signal, then apply a bias current and read the output. This is especially true when signal currents 1H1 and IH2 flow together, and if there is a time difference between them, a voltage state will occur when one signal current flows, and this will be held even when the other signal current flows. Not canceled (cancellation is done by reset)
It is from.
第1図A,b,c,dは対向電極接地型のジョセフソン
素子を説明する等価回路図、グラフ、断面図および概略
平面図、第2図A,bは本発明の実施例を示す概略平面
図および側面図てある。FIGS. 1A, b, c, and d are equivalent circuit diagrams, graphs, cross-sectional views, and schematic plan views illustrating a Josephson element with a grounded counter electrode. FIGS. 2A and b are schematic diagrams illustrating an embodiment of the present invention. A plan view and a side view are shown.
Claims (1)
電極を設け、該T字型の水平腕部の上を延び信号線を兼
ねる対向電極を設け、そして該水平腕部の両端において
該対向電極との間にジヨセフソン接合を形成させ、これ
らのジョセフソン接合の中間における該対向電極の前記
T字型の垂直脚部とは逆側の突出部をグランドプレーン
へ接続し、該基部電極の垂直脚部をバイアス電流入力お
よび信号出力端、前記対向電極の両端をそれぞれ信号入
力端としてなることを特徴とするジョセフソン素子を用
いた排他的論理和回路装置。1. A T-shaped base electrode is provided on the ground plane via an insulating layer, a counter electrode is provided that extends above the horizontal arm of the T-shape and also serves as a signal line, and the counter electrode is provided at both ends of the horizontal arm. A Josephson junction is formed between the Josephson junctions, and a protruding part of the opposing electrode opposite to the vertical leg of the T-shape in the middle of these Josephson junctions is connected to the ground plane. 1. An exclusive OR circuit device using a Josephson element, characterized in that the legs serve as bias current input and signal output terminals, and both ends of the counter electrode serve as signal input terminals.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55091371A JPS6051287B2 (en) | 1980-07-04 | 1980-07-04 | Exclusive OR circuit device using Josephson elements |
| US06/236,579 US4423430A (en) | 1980-02-20 | 1981-02-20 | Superconductive logic device |
| DE8181300724T DE3161996D1 (en) | 1980-02-20 | 1981-02-20 | Superconductive logic device incorporating a josephson junction |
| EP81300724A EP0035350B1 (en) | 1980-02-20 | 1981-02-20 | Superconductive logic device incorporating a josephson junction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55091371A JPS6051287B2 (en) | 1980-07-04 | 1980-07-04 | Exclusive OR circuit device using Josephson elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5717234A JPS5717234A (en) | 1982-01-28 |
| JPS6051287B2 true JPS6051287B2 (en) | 1985-11-13 |
Family
ID=14024511
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55091371A Expired JPS6051287B2 (en) | 1980-02-20 | 1980-07-04 | Exclusive OR circuit device using Josephson elements |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6051287B2 (en) |
-
1980
- 1980-07-04 JP JP55091371A patent/JPS6051287B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5717234A (en) | 1982-01-28 |
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