JPH0334868B2 - - Google Patents

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Publication number
JPH0334868B2
JPH0334868B2 JP60255089A JP25508985A JPH0334868B2 JP H0334868 B2 JPH0334868 B2 JP H0334868B2 JP 60255089 A JP60255089 A JP 60255089A JP 25508985 A JP25508985 A JP 25508985A JP H0334868 B2 JPH0334868 B2 JP H0334868B2
Authority
JP
Japan
Prior art keywords
magnetic field
field coupling
coupling lines
magnetic
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60255089A
Other languages
Japanese (ja)
Other versions
JPS62115881A (en
Inventor
Hideo Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP60255089A priority Critical patent/JPS62115881A/en
Publication of JPS62115881A publication Critical patent/JPS62115881A/en
Publication of JPH0334868B2 publication Critical patent/JPH0334868B2/ja
Granted legal-status Critical Current

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  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Logic Circuits (AREA)

Description

【発明の詳細な説明】 〔概 要〕 ジヨセフソン接合の寸法が同じで、磁界結合線
の数が異なる2種類以上の磁界結合型ジヨセフソ
ンゲート素子における、磁界結合線の配置の相違
による磁界結合度のばらつきを小さくするため
に、磁界結合線の本数の異なるゲート素子の磁界
結合線の配置を同一にした構成の磁界結合型ジヨ
セフソン集積回路を提起する。
[Detailed description of the invention] [Summary] Magnetic field coupling due to differences in the arrangement of magnetic field coupling lines in two or more types of magnetically coupled Josephson gate elements in which the dimensions of the Josephson junction are the same and the number of magnetic field coupling lines is different. In order to reduce the variation in magnetic field coupling, a magnetically coupled Josephson integrated circuit is proposed in which gate elements having different numbers of magnetic coupling lines have the same arrangement of magnetic coupling lines.

〔産業上の利用分野〕[Industrial application field]

本発明はジヨセフソン接合寸法が同一で、磁界
結合線の数が異なる2種類以上の素子よりなる磁
界結合型ジヨセフソン集積回路に関する。
The present invention relates to a magnetically coupled Josephson integrated circuit comprising two or more types of elements having the same Josephson junction dimensions and different numbers of magnetic coupling lines.

従来、多数の磁界結合線を持つたジヨセフソン
論理素子で論理積や、多数決ゲートを同一回路で
作製する際、磁界結合線の配置は特に考慮されて
いないため、磁界結合線の配置の相違による磁界
結合度のばらつきが大きく、その対策が望まれて
いる。
Conventionally, when fabricating logical products and majority gates in the same circuit in Josephson logic elements that have a large number of magnetic field coupling lines, the arrangement of the magnetic field coupling lines has not been particularly considered, so the magnetic field due to the difference in the arrangement of the magnetic field coupling lines There is a large variation in the degree of bonding, and countermeasures are desired.

〔従来の技術〕[Conventional technology]

第2図1,2はそれぞれ従来例による2/3多
数決ゲートと2入力論理積ゲートの磁界結合線の
配置を説明する平面図である。
2 are plan views illustrating the arrangement of magnetic field coupling lines of a conventional 2/3 majority gate and a two-input AND gate, respectively.

図において、11,21は鉛、あるいはニオブ
等の超伝導物質よりなる下部電極、12,22は
同じ超伝導物質よりなる上部電極、13,23は
ジヨセフソン接合領域、14,15,16,1
7、および24,25,26は磁界結合線であ
る。
In the figure, 11 and 21 are lower electrodes made of a superconducting material such as lead or niobium, 12 and 22 are upper electrodes made of the same superconducting material, 13 and 23 are Josephson junction regions, and 14, 15, 16, 1
7, and 24, 25, and 26 are magnetic field coupling lines.

磁界結合線は上部電極13,23の中央に集中
させて2/3多数決ゲートは4本、2入力論理積
ゲートは3本設けられている。
The magnetic field coupling lines are concentrated at the center of the upper electrodes 13 and 23, and four 2/3 majority gates and three two-input AND gates are provided.

両方のゲートの磁界結合線の1本は磁界のオフ
セツトをあたえるためのものである。
One of the magnetic field coupling lines for both gates is for providing a magnetic field offset.

磁界のオフセツトはこの磁界結合線に直流を流
して、適当な値に磁界のバイアスをあたえること
により行う。
Offset of the magnetic field is performed by applying a direct current to this magnetic field coupling line and biasing the magnetic field to an appropriate value.

この例の磁界結合線の配置では、2/3多数決
ゲートと2入力論理積ゲートの磁界結合度が異な
り、さらに中央に磁界結合線を設けた論理積ゲー
トでは中央の磁界結合線の磁界結合度が、他の2
本より大きくなり、同一ゲートの磁界結合線間で
の磁界結合度のばらつきが大きくなるという欠点
がある。
In the arrangement of the magnetic field coupling lines in this example, the degree of magnetic field coupling is different between the 2/3 majority gate and the two-input AND gate, and furthermore, in the AND gate with the magnetic field coupling line in the center, the degree of magnetic field coupling of the central magnetic field coupling line is different. But the other 2
It has the disadvantage that the magnetic field coupling degree is larger than that of the main gate, and the variation in the degree of magnetic field coupling between the magnetic field coupling lines of the same gate becomes large.

すなわち、第2図1と2では磁界結合線(磁界
制御線、あるいはコントロールラインとも呼ばれ
る)の位置が相違しており、従つて磁界感度が異
なり、本来、第2図1と2の回路は同一信号レベ
ルが入力されるため、各回路は同一レベルで応答
する特性とはならないで、動作マージンが小さく
なる。
In other words, the positions of the magnetic field coupling lines (also called magnetic field control lines or control lines) are different in Figure 2 1 and 2, and therefore the magnetic field sensitivity is different, and the circuits in Figure 2 1 and 2 are originally the same. Since the signal level is input, each circuit does not have the characteristic of responding at the same level, and the operating margin becomes small.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の、ジヨセフソン接合寸法が同一で、磁界
結合線の数が異なる2種類以上の素子よりなる磁
界結合型ジヨセフソン集積回路においては、磁界
結合度のばらつき(差)が大きく、回路の動作マ
ージンが小さい。
In conventional magnetically coupled Josephson integrated circuits, which are made up of two or more types of elements with the same junction dimensions and different numbers of magnetic coupling lines, variations (differences) in the degree of magnetic coupling are large and the circuit operating margin is small. .

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点の解決は、ジヨセフソン接合寸法が
略同一で、磁界結合線の数が異なる2種類以上の
素子よりなる磁界結合型ジヨセフソン集積回路に
おいて、 磁界結合線の数が最大の第1の本数である第1
の素子と、 磁界結合線の数が該第1の素子より少ない第2
の本数である磁界結合線と、第1の本数と第2の
本数の差分に相当する本数を仮想的に設けた仮想
磁界結合線とが、該第1の素子上に設けられる磁
界結合線の配置と略同一であり、かつ電極の中央
には磁界結合線を配置しない第2の素子とを有す
ることを特徴とする磁界結合線ジヨセフソン集積
回路により達成される。
The solution to the above problem is that in a magnetically coupled Josephson integrated circuit consisting of two or more types of elements with approximately the same junction dimensions and different numbers of magnetic coupling wires, the first number of magnetic coupling wires has the largest number. a certain first
and a second element having fewer magnetic field coupling lines than the first element.
of magnetic field coupling lines provided on the first element, and virtual magnetic field coupling lines whose number corresponds to the difference between the first number and the second number. This is achieved by a magnetic field coupling line Josephson integrated circuit having a second element having substantially the same arrangement as the magnetic field coupling line and a second element in which no magnetic field coupling line is disposed in the center of the electrode.

特に、1本の磁界オフセツト用磁界結合線と、
3、および2本の入力信号用磁界結合線をそれぞ
れ同一寸法を有するジヨセフソン接合上に配設し
て2/3多数決ゲート素子、および2入力論理積
ゲート素子を形成する際に、磁界結合線をそれぞ
れのジヨセフソン接合の中央に対して対称に2本
ずつ、およびその内の1本を除いた配置で設けて
なる磁界結合型ジヨセフソン集積回路において、
発明の効果は大きい。
In particular, one magnetic field coupling line for magnetic field offset,
When forming a 2/3 majority gate element and a 2-input AND gate element by arranging 3 and 2 input signal magnetic field coupling lines on Josephson junctions having the same dimensions, the magnetic field coupling lines are In a magnetically coupled Josephson integrated circuit in which two Josephson junctions are arranged symmetrically with respect to the center of each Josephson junction, and one of them is removed,
The effects of invention are significant.

〔作 用〕[Effect]

本発明はジヨセフソン接合寸法が同一で、磁界
結合線の数が異なる2種類以上の素子よりなる磁
界結合型ジヨセフソン集積回路においては、各素
子ごとに磁界結合線の配置を同一にすることによ
り磁界感度差を小さくできることを実験的に確か
めて、論理回路に適用したものである。
The present invention provides a magnetically coupled Josephson integrated circuit consisting of two or more types of elements with the same junction dimensions and different numbers of magnetic coupling lines, which improves magnetic field sensitivity by making the arrangement of the magnetic coupling lines the same for each element. It was experimentally confirmed that the difference could be reduced and applied to logic circuits.

特に、磁界結合線は接合中央においては磁気感
度が大きくなつてしまうので、中央部を避けて配
置した。
In particular, the magnetic field coupling line has a high magnetic sensitivity at the center of the junction, so it was arranged to avoid the center.

〔実施例〕〔Example〕

第1図1,2はそれぞれ本発明による2/3多
数決ゲートと2入力論理積ゲートの磁界結合線の
配置を説明する平面図である。
1 and 2 are plan views illustrating the arrangement of magnetic field coupling lines of a 2/3 majority gate and a two-input AND gate, respectively, according to the present invention.

実施例においても、第2図の従来例と対比し
て、回路構成は簡明のために上記の組み合わせを
採用する。
In this embodiment as well, in contrast to the conventional example shown in FIG. 2, the above combination is adopted for the circuit configuration for simplicity.

図において、11,21は鉛、あるいはニオブ
等の超伝導物質よりなる下部電極、12,22は
同じ超伝導物質よりなる上部電極、13,23は
ジヨセフソン接合領域、14,15,16,1
7、および24A,25A,26Aは磁界結合線
である。
In the figure, 11 and 21 are lower electrodes made of a superconducting material such as lead or niobium, 12 and 22 are upper electrodes made of the same superconducting material, 13 and 23 are Josephson junction regions, and 14, 15, 16, 1
7, and 24A, 25A, and 26A are magnetic field coupling lines.

第1図1の2/3多数決ゲートは第2図1の従
来例と同じであるが、第1図2の論理積ゲートの
磁界結合線の配置を2/3多数決ゲートの4本の
磁界結合線の内の3本と同一にしている。
1. The 2/3 majority gate in FIG. 1 is the same as the conventional example in FIG. 1, but the arrangement of the magnetic field coupling lines of the AND gate in FIG. It is made the same as three of the lines.

また、第1図2では最も下の磁界結合線を除い
たが、他のどれを除いてもよい。
Further, in FIG. 1 and 2, the lowermost magnetic field coupling line is removed, but any other line may be removed.

このような配置にすることにより、2種類のゲ
ートの磁界結合線の配置が同一になるとともに、
磁界感度が特別よい上部電極の中央に磁界結合線
を配置することが避けられ、磁界結合度のばらつ
きを低減でき、回路の動作マージンを大きくする
ことができる。
By making this arrangement, the arrangement of the magnetic field coupling lines of the two types of gates becomes the same, and
It is possible to avoid arranging the magnetic field coupling line in the center of the upper electrode, which has particularly high magnetic field sensitivity, and it is possible to reduce variations in the degree of magnetic field coupling and increase the operating margin of the circuit.

第3図はジヨセフソン素子の構造を説明するA
−A断面図である。
Figure 3 is A explaining the structure of Josephson device.
-A sectional view.

図において、1は薄いアルミナ層等よりなるト
ンネル接合で、それぞれ超伝導物質よりなる下部
電極21と上部電極22間に形成されてジヨセフ
ソン接合を構成する。
In the figure, reference numeral 1 denotes a tunnel junction made of a thin alumina layer or the like, which is formed between a lower electrode 21 and an upper electrode 22 each made of a superconducting material to form a Josephson junction.

2はジヨセフソン素子の領域23を画定する厚
い絶縁層である。
2 is a thick insulating layer defining a region 23 of the Josephson element.

磁界結合線24A,25A,26Aは上部電極
22の上に絶縁層3を介して形成される。
The magnetic field coupling lines 24A, 25A, and 26A are formed on the upper electrode 22 with the insulating layer 3 interposed therebetween.

つぎに、以上の例で説明した異なる種類のゲー
トで構成された回路例として、全加算器について
述べる。
Next, a full adder will be described as an example of a circuit configured with the different types of gates explained in the above example.

第4図1,2はジヨセフソン素子による電流フ
リツプフロツプを用いた全加算器の回路図であ
る。
FIGS. 4 1 and 2 are circuit diagrams of a full adder using a current flip-flop based on Josephson elements.

第4図1は和信号発生回路、第4図2は桁上げ
信号発生回路を示す。
FIG. 41 shows a sum signal generation circuit, and FIG. 42 shows a carry signal generation circuit.

全加算器を超伝導ループからなる電流フリツプ
フロツプで構成する際の一例として、和信号So
桁上げ信号Coは、それぞれつぎのような論理で
実現できる。
As an example of configuring a full adder with a current flip-flop consisting of a superconducting loop, the sum signal S o ,
The carry signal C o can be realized using the following logic.

So=Ao(Bo o-1o(Co-1) +o(BoCo-1o o-1)、 oo(Bo o-1oCo-1) +Ao(BoCo-1o o-1)、 Co=AoBo+Co-1(Ao+Bo)、 oo oo-1oo). ここで、Ao、Boは入力信号、Co-1は前段から
の桁上げ信号である。
S o = A o (B o o-1 + o (C o-1 ) + o (B o C o-1 + o o-1 ), o = o (B o o-1 + o C o-1 ) +A o (B o C o-1 + o o-1 ), C o = A o B o +C o-1 (A o +B o ), o = o o + o-1 ( o + o ).Here Here, A o and B o are input signals, and C o-1 is a carry signal from the previous stage.

和信号Soは上記の論理通りに、論理和と論理積
ゲートで構成できる。
The sum signal S o can be constructed from a logical sum and an AND gate according to the above logic.

桁上げ信号Coは上記の論理通りでも実現でき
るが、回路の段数を低減するために、2/3多数
決ゲート1段で実現できる。
The carry signal C o can be realized according to the above logic, but in order to reduce the number of circuit stages, it can be realized with one stage of 2/3 majority gate.

すなわち、2/3多数決ゲートは入力信号Ao
Bo、および前段からの桁上げ信号Co-1の3入力
の内2つ以上が“1”であれば桁上げ信号Co
“1”となる動作を行う。
That is, the 2/3 majority gate receives the input signal A o ,
If two or more of the three inputs of B o and the carry signal Co -1 from the previous stage are "1", the carry signal Co becomes "1".

図において、各ループはそれぞれの分枝にジヨ
セフソン接合を有する電流フリツプフロツプであ
る。
In the figure, each loop is a current flip-flop with Josephson junctions in its respective branches.

×印はジヨセフソン接合(JJであらわす)、矢
印とコの字型の記号は磁界結合線をあらわし、こ
こに上記の入力信号があたえられる。
The x mark represents a Josephson junction (represented by JJ), and the arrow and U-shaped symbol represent a magnetic field coupling line, to which the above input signal is applied.

この場合、2入力の論理積ゲートと2/3多数
決ゲートはすべての磁界結合線のしきい値〔ジヨ
セフソン接合に超伝導電流を流すことができる制
御電流(磁界結合線に流す電流)の限界値〕を同
一にすることが望まれるため、本発明による第1
図の構造を採用した。
In this case, the 2-input AND gate and the 2/3 majority gate are used to determine the threshold value of all magnetic coupling lines [the limit value of the control current (current flowing through the magnetic coupling lines) that allows superconducting current to flow through the Josephson junction. ] is desired to be the same, so the first method according to the present invention
The structure shown in the figure was adopted.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように本発明によれば、ジ
ヨセフソン接合寸法が同一で、磁界結合線の数が
異なる2種類以上の素子よりなる磁界結合型ジヨ
セフソン集積回路においては、磁界結合度のばら
つきが小さく、回路の動作マージンが大きい。
As explained in detail above, according to the present invention, in a magnetically coupled Josephson integrated circuit comprising two or more types of elements with the same Josephson junction dimensions and different numbers of magnetic coupling lines, variations in the degree of magnetic coupling are small. , the circuit has a large operating margin.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図1,2はそれぞれ本発明による2/3多
数決ゲートと2入力論理積ゲートの磁界結合線の
配置を説明する平面図、第2図1,2はそれぞれ
従来例による2/3多数決ゲートと2入力論理積
ゲートの磁界結合線の配置を説明する平面図、第
3図はジヨセフソン素子の構造を説明する第1図
のA−A断面図、第4図1,2はジヨセフソン素
子による電流フリツプフロツプを用いた全加算器
の回路図である。 図において、11,21は下部電極、12,2
2は上部電極、13,23はジヨセフソン接合領
域、14,15,16,17,24A,25A,
26Aは磁界結合線である。
1 and 2 are plan views illustrating the arrangement of magnetic field coupling lines of a 2/3 majority gate and a two-input AND gate according to the present invention, respectively, and FIGS. 2 1 and 2 are 2/3 majority gates according to the conventional example, respectively. 3 is a cross-sectional view taken along the line A-A in FIG. 1 to explain the structure of the Josephson device, and FIG. 4 1 and 2 are the currents generated by the Josephson device. FIG. 2 is a circuit diagram of a full adder using flip-flops. In the figure, 11 and 21 are lower electrodes, 12 and 2
2 is the upper electrode, 13 and 23 are Josephson junction regions, 14, 15, 16, 17, 24A, 25A,
26A is a magnetic field coupling line.

Claims (1)

【特許請求の範囲】 1 ジヨセフソン接合寸法が略同一で、磁界結合
線の数が異なる2種類以上の素子よりなる磁界結
合型ジヨセフソン集積回路において、 磁界結合線の数が最大の第1の本数である第1
の素子と、 磁界結合線の数が該第1の素子より少ない第2
の本数である磁界結合線と、第1の本数と第2の
本数の差分に相当する本数を仮想的に設けた仮想
磁界結合線とが、該第1の素子上に設けられる磁
界結合線の配置と略同一であり、かつ電極の中央
には磁界結合線を配置しない第2の素子とを有す
ることを特徴とする磁界結合線ジヨセフソン集積
回路。
[Scope of Claims] 1. In a magnetically coupled Josephson integrated circuit comprising two or more types of elements with substantially the same junction dimensions and different numbers of magnetic coupling lines, the first number of magnetic coupling lines is the largest. a certain first
and a second element having fewer magnetic field coupling lines than the first element.
of magnetic field coupling lines provided on the first element, and virtual magnetic field coupling lines whose number corresponds to the difference between the first number and the second number. A second element having substantially the same arrangement as the magnetic field coupling line and a second element having no magnetic field coupling line disposed in the center of the electrode.
JP60255089A 1985-11-15 1985-11-15 Magnetic field coupling type josephson integrated circuit Granted JPS62115881A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60255089A JPS62115881A (en) 1985-11-15 1985-11-15 Magnetic field coupling type josephson integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60255089A JPS62115881A (en) 1985-11-15 1985-11-15 Magnetic field coupling type josephson integrated circuit

Publications (2)

Publication Number Publication Date
JPS62115881A JPS62115881A (en) 1987-05-27
JPH0334868B2 true JPH0334868B2 (en) 1991-05-24

Family

ID=17273971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60255089A Granted JPS62115881A (en) 1985-11-15 1985-11-15 Magnetic field coupling type josephson integrated circuit

Country Status (1)

Country Link
JP (1) JPS62115881A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0810772B2 (en) * 1988-02-10 1996-01-31 シャープ株式会社 Ceramic superconducting device
JPH0810770B2 (en) * 1988-02-10 1996-01-31 シャープ株式会社 Ceramic superconducting device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS589381A (en) * 1981-07-08 1983-01-19 Hitachi Ltd Josefson logic circuit

Also Published As

Publication number Publication date
JPS62115881A (en) 1987-05-27

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