JPS6055749A - Line monitor system - Google Patents

Abstract

PURPOSE:To extend a line monitor range by comparing data subjected to synchronous switching and speed conversion with a preliminarily extracted parity P bit to obtain an error pulse in a digital time division multiplex radio line of non-instantaneous break switching system. CONSTITUTION:Parity P bits are extracted from signals DATA1, DATA2, and CLK of a stand-by line and a current line, and one of them is selected by a selecting circuit 39. Output data obtained by switching signals of the stand-by line and the current line synchronously in accordance with switching of the selecting circuit 39 and subjecting them to speed conversion are integrated for every frame. Obtained data P' is compared with the selected parity bit, and the error pulse is generated if they do not coincide with each other. Consequently, a PLL circuit for clock generation is shared between a synchronous switching circuit and a speed converting circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a line monitoring system for performing a parity check on a digital wireless line that performs instantaneous switching between working and protection lines.

Prior Art and Problems In digital time-division multiplexing radio lines, the line is switched to the backup line during maintenance and inspection of the working line, and when the working line is restored, the line is switched from the protection line to the working line again. However, in order to avoid interrupting the data being transmitted during such switching, it is necessary to carry out uninterrupted switching, and for this reason, uninterrupted line switching is used.

FIG. 1 illustrates a no-interruption switching system in a digital time-division multiplexed radio line. In the same figure, 101~
105 indicates the working lines of systems 1 to n, respectively;
00 is a protection line. In the working line 101, an input signal from a multiplexer (not shown) is divided into two by the hybrid 1, one signal is applied to the bipolar-unipolar conversion circuit 5 of the working line, and the other signal is applied to the changeover switch 2.
It is normally consumed by the load R, but when switching to the protection line is performed, it is added to the bipolar-unipolar conversion circuit 6 of the protection line. The bipolar-unipolar conversion circuits 6 of both lines convert the input bipolar signal into a unipolar signal, and the stuff circuit 4 converts the speed of this signal, and then inserts a control bit such as a frame synchronization pulse, that is, a stuff pulse. The PCM transmitter 5 transmits this as m@PCM
Convert it to a modulated signal and send it out. PCM receiver (i-machine 6 receives and demodulates this via the transmission line. Frame synchronization circuit 11 performs frame synchronization with the demodulated signal and extracts the inserted stuff pulse. Synchronization switching and speed conversion circuit 1
2 performs synchronous switching to divide the input signal in response to the 2m phase PCM signal and write each into the buffer memory, and further performs speed conversion by sequentially reading out each buffer memory output to generate a unipolar signal. Play. The unipolar-bipolar conversion circuit 8 converts unipolar signals into bipolar signals.

A selector switch 9 selects the outputs of both the current and standby unipolar-bipolar converter circuits and inputs the selected outputs to a multiplexer/demultiplexer (not shown).

In the wireless line shown in FIG.
Mechanical relays are used due to the 41 degree of reliability, but
This is currently used because the operating speed is slow.

Switching the standby will cause a momentary interruption. Therefore, in FIG. 1, a data switching circuit 10 is provided to select the stuff circuit output of each working line and protection line and connect it to the PCM transmitter 5 of the protection line, and a distribution circuit 15 is provided to select the stuff circuit output of each working line and protection line. data, clock, and frame synchronization pulses are distributed to the synchronization switching and speed conversion circuits of each working line and protection line. For example, when switching from the working line 101 to the protection line 100, the changeover switches 2 and 9 are A path from the hybrid 1 to the data switching circuit 10 via the backup line is formed by switching the synchronous switching and speed conversion circuit 12 to the output, and then the data switching circuit 10 and the distribution circuit 16 are switched. When the protection line 100 is activated, the data switching circuit and the distribution circuit are composed of electronic circuits and operate at high speeds, so there is no momentary interruption caused by switching. It is possible to perform instantaneous line switching. Such an uninterrupted switching system for digital time-division multiplexing radio lines is disclosed in Japanese Patent Application No. 54-50927 (1983).
This method is already known from Japanese Patent Application Laid-open No. 143850/1983.

However, in the uninterrupted switching system shown in FIG. 1, no consideration is given to performing a parity check for line monitoring. FIG. 2 shows an example of a frame format when performing a parity check on a digital time-division multiplex radio channel.

The same figure shows a case where a 4-phase PSE signal is used as a transmitting and receiving end signal, and the QII DATAl and DATA2 (2n+1) bits of two channels from the carrier end station equipment are set to 157L'-A, and the frame synchronization bit F is set to 157L'-A.
, a parity bit P is added. Parity bit pi.

P2. ... is added every 1 s frame on the sending end side [: (2&+1) (2&+1)') and is inserted at the position of the P timing pulse that has the same period as the frame synchronization pulse F.

Further, FIG. 6 shows an example of a parity check circuit provided on the receiving side, and shows two channels of data DATA1' and DATA1'.
, ITA2' are integrated every 1S frame in the data integration circuit 21 to obtain the output P', and the P bit extraction circuit 22
In the comparison circuit 25, the output P' and the parity bit P extracted from the receiver 41 count are compared using the P timing pulse extracted from the take DATA 2', and if they do not match, the data DATAI', D.A.
Assuming that there is a bit error in TA 2', an error pulse is generated. Here, the data with a dash indicates that the data is taken via the wireless line and contains errors. Note that in the case of the frame format shown in FIG. 2, the integration in the data integration circuit 2 is performed for each time slot as shown. This is because modulation is performed using differential logic in the 4-phase PSK modulation circuit on the transmitting side, so if a 1-bit error occurs in the wireless line, an error will also occur in the next time slot, so it seems that the integration is performed for each bit. This is because the parity check cannot be performed correctly. In this way, the integrity check is P
This is generally done before speed conversion because it needs to be done by extracting bits.

FIG. 4 shows an example of a configuration in which a parity check is performed on the receiving side of the wireless line of the instantaneous interruption switching system shown in FIG. In the figure, a frame synchronization circuit 111 and a distribution circuit 15 for the working line and protection line are the same as those shown in FIG. 14 is a synchronous switching circuit; 15 is a speed conversion circuit; these are divided functions of the synchronous switching and speed conversion circuit 12 in FIG. 1; is written to the buffer memory in each phase and read out using a common clock.The speed conversion circuit 15 performs speed conversion to convert the output of each rougher memory from which the stuff pulse has been removed into a continuous output. I do.

16 is a parity check circuit, which is a synchronous switching circuit 14
It is provided at the subsequent stage of the synchronous switching circuit 14, and can perform a parity check on the data up to the synchronous switching circuit 14. However, in this case, it is necessary to provide the speed conversion circuit 15 at the subsequent stage of the check process circuit 16. In order to create the speed conversion clock in the conversion circuit 15, a phase locked loop (PLL) circuit is required, so if the configuration shown in FIG. 4 is adopted, two sets of PLL circuits are required. Become.

FIG. 5 shows an example of a configuration in which a parity check is performed on the receiving side of the wireless line of the no-interruption switching method shown in FIG. In the figure, frame synchronization circuit 11. The synchronous switching and speed conversion circuit 122 distribution circuit 16 is the same as that shown in FIG.

In FIG. 5, check circuits 16A and 16B are provided after the frame synchronization circuit 11 of the working line and the protection line, respectively.
The output signal of is added to the distribution circuit 16. The distribution circuit 16 is
The cheater block and frame synchronization pulse of the frame synchronization circuit 11 of the protection line are supplied to the synchronization switching and speed conversion circuit 12, and the synchronization switching and speed conversion circuit 12 thereby performs synchronization switching with respect to the output signal of the parity check circuit 16B. , speed conversion is performed and Uniborai I is reproduced. In this case, since the synchronization switching circuit and the speed conversion circuit are integrated into the same circuit, there is an advantage that only one PLL circuit is required for clock generation, but on the other hand, the parity check circuits 16A and 16B are Therefore, it is not possible to monitor the occurrence of errors in the synchronization switching and speed conversion circuit 12 and the distribution circuit 15, and the range of monitoring by parity check becomes narrow.

OBJECT OF THE INVENTION The present invention attempts to solve the problems of the prior art, and its purpose is to perform a quality check (on the receiving end side of a digital time division multiplexed radio line of an uninterrupted switching system). To provide a line monitoring method that allows the monitoring range to include one speed conversion circuit without requiring two sets of clock generation PLL circuits for synchronization switching and speed conversion. It is in.

Embodiment of the Invention FIG. 6 shows the configuration of an embodiment 91 of the line monitoring system of the invention. In the figure, only the narrow part of the four receiving screens is shown, and 51 and 52 are frame synchronization circuits for the working line and protection line, respectively, 66 is a first period switching board, and 54 is a distribution board. Further, in the synchronization switching board 66, 65 is a synchronous switching and speed conversion circuit, 66 is a data integration circuit, and 6
7 is a P bit extraction circuit, 69 is a switch (5F), 40
is a comparison circuit, and 68 in the distribution board 34 is a P bit extraction circuit.

In FIG. 6, Kerr seconds 11 is shown in the case of the four-phase PSK system, as explained in FIG. 2 and subsequent figures. Frame synchronization circuits 31 and 32 receive the clock CLK generated for data DATA i , DATA 2 and 'AIJ of the working line and protection line, respectively, and extract frame synchronization pulses and P timing pulses. Each signal output from the frame synchronization circuit 32 of the protection line is distributed to the synchronization switchboards of each working line via a distribution board 64. In the synchronous switching board 63, the synchronous switching and speed conversion circuit 65 selects the frame synchronous circuit output of the working line or the protection line in response to a switching command, and performs synchronous switching and speed conversion similarly to the synchronous switching and speed conversion circuit 12 in FIG. Then, two channels of data DATAIA and DATA2A consisting of unipolar signals and a clock CLKA corresponding to these signals are output. Each of these signals is sent to a demultiplexer via a changeover switch (not shown). Further, the data integration circuit 56 uses the P timing pulse as described in FIG. 5 to perform integration for every IS7 frame at every other time slot to obtain an output P'.

, On the other hand, the P bit extraction circuit 37 is connected to the frame synchronization circuit 61.
The P bit of the working line is extracted by the data D, 4 TA 2 output and the P timing pulse.

Similarly, the P bit extraction circuit 68 extracts the P bit of the protection line based on the data DATA2 output of the frame synchronization circuit 62 and the P timing pulse. The switch 69 selects the P bit output of the P bit extraction circuit 67 or the P pit extraction circuit 68 in response to a switching command. Comparison circuit 40 compares the P' output of data integration circuit 66 and the P bit output of switch 69, and generates an error pulse when they do not match.

In this way, in the method of the present invention, after switching the data of the working line and the reserve line and performing synchronous switching and speed conversion, data) tjk calculation is performed, and the data extracted in advance before synchronous switching and speed conversion are performed. Since the error pulse is obtained by comparing with the P bit, it is possible to not only perform error monitoring including synchronous switching and speed conversion circuits, but also
By using the PLL circuit for generating the clock f't in common with the synchronous switching circuit and the four speed conversion circuits, there is an advantage that only one set of PLL circuits is required.

As described in detail, according to the line monitoring system of the present invention, the remaining bits are extracted from the signals of the protection line and the working line, and one of them is selected by the selection circuit, and the signal of the working line and the protection line is The selected parity bit is compared with the data obtained by integrating the output data for each frame after speed conversion by switching the signal in synchronization with the switching of the selection circuit. Since this design generates an error pulse when switching between the working line and the standby circuit, it is possible to combine the synchronous switching circuit and the speed conversion circuit into one without providing clock generation PLL circuits for each. This is not only economical, but also shortens the synchronization pull-in time, and since the speed conversion circuit is included in the arrangement, the line monitoring range can be expanded.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining an instantaneous interruption switching method in a digital time division multiplexing radio line, FIG. 2 is a diagram showing an example of a 7-frame format when performing a parity check in a digital time division multiplexing radio line, FIG. 5 is a diagram showing an example of a parity check circuit provided on the receiving side, FIGS. 4 and 5 are diagrams each showing a configuration example of a conventional line monitoring system in an uninterrupted switching wireless line, and FIG. 1 is a diagram showing the configuration of an embodiment of a line monitoring system of the present invention. 1...Hybrid, 2...Selector switch, 6...
・Bipolar unipolar conversion circuit, 4... Stuff circuit, 5... PCM transmitter, 6... PCM receiver, 8...
... Unipolar bipolar conversion circuit, 9... Changeover switch, 10... Data switching circuit, 11... Frame synchronization circuit, 12... Synchronization switching and speed conversion circuit, 1
6... Distribution circuit, 14... Synchronous switching circuit, 1S...
・Speed conversion circuit, 16° 16.4.16fl...Parity check circuit, 21...Data integration circuit, 22.
... P bit extraction circuit, 26... Comparison circuit, 31.3
2...Frame synchronization circuit, 66...Synchronization switch board, 6
4...Distribution board, 65...Synchronization switching and speed conversion circuit, 56...Data integration circuit, 37.58...P pit extraction circuit, 39...Switch (SF), 40...
・Comparison circuit, 100...protection line, 101~10fi
... Current line patent applicant Gobe Tamamushi, patent attorney representing Fujitsu Limited (1 other person)

Claims (1)

[Claims] On the receiving end side of a digital time division multiplexed radio line having a working line and a protection line, a protection side parity bit extraction circuit extracts and outputs a parity bit from the signal of the protection line, and a protection side parity bit extraction circuit extracts the parity bit from No. 48 of the working line. A working side parity bit extraction circuit that extracts and outputs the parity bit extraction circuit, a selection circuit that switches and outputs the output of the protection side and working side parity bit extraction circuits, and a switching circuit that synchronously switches between the protection line signal and the working line signal. A synchronous switching/speed conversion circuit that performs speed conversion, a data integration circuit that integrates the output data of the synchronous switching/speed conversion circuit for each frame, and a comparison between the output data of the data integration circuit and the output data of the selection circuit. and a comparison circuit that generates an error pulse when the signals do not match.