JPS6055858B2 - interface circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interface circuit for controlling bidirectional communication between a keyboard and a data processing device, and more particularly to an interface circuit for controlling bidirectional communication between a keyboard and a data processing device, and in particular for controlling such communication using only two wires between the interface circuit and the keyboard. The present invention relates to a self-based interface circuit that enables one communication.

Keyboard entry control or interface circuits are known in the art, but these are very complex and require more than two wires between the keyboard and the interface circuit.

That is, it requires two wires carrying clock and data signals, plus a status line to indicate the status of the keyboard and central processing unit. A conventional keyboard entry control circuit and interface circuit is disclosed in U.S. Pat.
No. 01479, No. 3533078, No. 4038640
No. 4044398, No. 4126898 and No. 4
No. 170768. An object of the present invention is to eliminate the need for a conventionally complicated keyboard interface circuit, and to provide only two wires between the interface circuit and the keyboard. The features of the present invention are as follows.

1 Keyboard Data Rate and Clock Operation can send data at any rate without being tied to a particular clock frequency.

2 The only time relationship required is the setup and hold time required in relation to the rising edge of the keyboard clock.

Such relationships can be easily implemented in microcode.
3 can support bidirectional communication between the central processing unit (CPU) and the keyboard of the data processing system.

4 Complete initial connection and synchronous operation.

5. The number of components is small compared to conventional interface circuits.

The presence of one or the other of two voltage levels on the two lines connecting the keyboard and the interface circuitry causes operations to control the transmission of keyboard data and the reset of the keyboard.

ζ Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing a data processor, ie, a small computer, such as a so-called personal computer.

In this figure, a three-state system bus 10 containing z-address, data, and control lines interconnects the basic components of the computer to effect the necessary transfer of address, data, and control signals between the components. Basic components include, for example, a central processing unit (CPU) 12
,for example? ×8 dynamic random access memory (R
AM) 1×Multi-channel programmable direct memory●
access (DMA) control device 16, interrupt control device 18,
Included are read only storage (ROS) 20, DI/DO 22, display adapter 24, disk adapter 26, and keyboard interface circuitry 28. Cathode ray tube display 30 is connected to display adapter 24 via cable 32 . A pair of diskette drives 34
and 36 connects disk adapter 2 by cable 38.
Connected to 6. Keyboard 40 is connected to keyboard interface 28 by cable 42. C
PUl2 is, for example, I of Santa Clara, California.
6 published by ntelCOrpOratiOn
6The8086FamilyUser'SManaa
Fully disclosed in October 979
Constructed by nteImicrOprOcessOr8O88.

The DMA controller, for example, also has the above 1nte1C.
It is constructed with an Intel 823 performance programmable DMA controller, which is fully disclosed in the 0rp0rati0n publication. The RAMl4 is constituted by a general dynamic memory such as TI4ll6. The interrupt control device 18 is composed of, for example, an Intel 8259 chip. ROS2O is, for example, MOstek's MK
It is configured by a general read-only device such as 36OO. The DI/DO 22 is configured by a digital input/digital output interface, such as the Ntel 8255A general purpose programmable peripheral interface chip. Keyboard interface circuit 2
Eight embodiments or embodiments of the invention are shown in FIG.

Keyboard 40 is a programmable self-scanning serializing keyboard that delivers scan codes consisting of eight serial data bits identified at various key positions.

The scan codes include a start bit, and each serial scan code is contained in a 9-bit frame preceded by the start bit. The keyboard 40 can be of the capacitive matrix type, for example, and has eight key positions. can have. The keyboard 40 is, for example, an Intel8O keyboard.
Contains its own microprocessor such as 48, clock output line 0, clock sense line SC, data output line 0
It has a D1 data sensing line SD. Furthermore, each key is capable of make/break and continuous operations. The keyboard includes self-scanning logic and interface controllers that support protocols for the keyboard interface circuit 28. The keyboard 40 itself does not form part of the present invention and will not be described in detail here.

The structure and circuit of the keyboard is disclosed in U.S. Patent No. 378,649.
No. 7, No. 3921167 and No. 4118611. Generally, keyboard interface circuit 28 is self-running or operates based on its own clock. In other words, the keyboard interface circuit 28 operates completely independently of any other clock speed of the computer or data processing device.
Generates clock and data. When the system bus sends a reset command to the keyboard in response to power up or the interface circuitry has not processed the previous scan code frame, the keyboard is inhibited from having its control logic transmit data. Complete scan code●
If the frame is stored in the interface circuit, the latch sends an interrupt request signal 1R to the CPU via the interrupt controller. When the interrupt request is granted and the data is transferred to the CPU, the latch is cleared or reset, indicating to the keyboard via the data line that another scan code can be transmitted to the interface circuit. Only two wires are required in the cable connecting the interface circuit to the keyboard for all data transmission, clocking, and situational awareness. Next, a more detailed explanation will be given with reference to FIG. Clock sense line 50 is connected to keyboard clock output line 52 at connection point 54 and is connected to an open collector gate (e.g., Texas I
``TheTTLData'' published by nstruments
SN74O shown in BOOk8 2nd edition, 197th edition
7) is connected between the connection point 54 and the other end of the clock output line 51, one end of which is connected to the keyboard control logic.

Additionally, the keyboard data sense line 57 is connected to the data output line 58 at a connection point 60, and another open collector (0C) gate 61 connects the other end of the data output line 59 with one end connected to the keyboard control logic. Connection point 60
is connected between. A cable 42, containing only a clock line 52 and a data line 58, connects the keyboard 40 to the keyboard interface circuit 28. The interface circuit 28 itself requires only four wires: the keyboard clock and data lines, and the +5 volt (+5V) and ground (GND) or zero volt lines. Interface circuit 28 includes a series-to-parallel shift register (e.g.,
Encoder 62 includes nine stages and eight corresponding data output lines A,
B, C, D, E, F, G, H and a start line h''.

Stage h'' is the top stage and stage A is the bottom stage. The top stage output line h'' is connected to the D input terminal of the D-type edge trigger latch 68. Clock line 52 is connected to a clock terminal CLK of latch 68. Q of latch 68
That is, the set output terminal is connected to the system bus 10 and sends an interrupt request signal 1R to the CPU12 via the interrupt control device 18. The Q or reset output line of latch 68 is connected to another open collector gate (0C) gate 7.
0 to the keyboard data line 58. The clear or reset terminal of latch 68 is also connected to system bus 10 so that the interrupt request is acknowledged and the eight parallel data bits from encoder 62 are output to DI/DO.
22 to the register of the CPU, it receives a clear or reset signal from the CPU. 0 gate 56
, 61 and 70 are operatively switched to bring the lines to which their outputs are connected to ground potential, or zero voltage, when closed.

In other words, when the gate input is ゜゜1゛, or a high level, the gate output is ゜゜1゛, or a high level (5V). This will be explained with reference to the figures.

First, it is assumed that +5 volts are applied to the clock line 52 and the data line 58. The line is said to be in a high level state when a voltage of +5 volts is applied to the line, and the line is said to be in a low level state when the lightning voltage on the line is 0 volts or at ground potential. keyboard 40
When the key is pressed, a clock output signal (1) and a data output signal 0D are generated. Initially, the keyboard sets its clock output signal to “゜1”. Thereafter, the keyboard outputs the clock line 52 via the clock sense line 50 to sense whether the clock line 52 is in a high or low level state. Sensing the condition: If the clock line 52 is in a low state, the system causes the keyboard 40 to perform a reset by providing a ground signal RST (programmable) from the DI/DO 22 to the reset line 72.
request. This state occurs in response to power-up,
Forces the keyboard to reset all its circuits. However, when keyboard 40 senses a high state on clock line 52, it attempts to force data line 58 into a high state. Keyboard 40 tests or senses the state of data line 58 via data sense line 57 .

With data line 58 in a low state, the computer or data processing device did not process the previous scan code sent to interface circuit 28 and the Q output of latch 68 remained low or "0". Eventually, the keyboard 40 is suppressed and the data line 58 becomes ゜゜1.
In other words, wait for it to reach a high level. When data line 58 goes high, keyboard 40 consists of eight serial data bits representing a scan code representing a particular key on the keyboard, followed by a start bit;
The bit frame is sent out on line 58. As shown in FIG. 3, the start and eight data bits are shifted into a nine stage encoder 62 under control of keyboard clock output 0.

(SB in FIG. 3 indicates the start bit.) Clock output 0C need not be periodic; the data bits follow clock output 0C. Therefore, the interface circuit 28 is not bound to any clock frequency in the system and is based on the keyboard 40. During transmission of scan code frames over data line 58, interface circuit 28 operates under the control of keyboard 40, with latch 68 in a clear or reset state and the Q output high; is also at a high level. Once all nine bits of the scan code frame have been shifted into encoder 62, the start bit of the most significant stage is clocked by clock output 0C and applied to the D input of latch 68.

As a result, the latch 68 is set, the Q output becomes high level, and the interrupt request signal 1R is sent to the system bus, and the Q
The output is at a low level, and therefore the data line 58 is at ground potential. Keyboard 40 senses a low level condition on data line 58 via data sense line 57, thus inhibiting further data transmission. However, after the interrupt request is acknowledged and the eight data bits are transmitted in parallel from encoder 62 to system bus 10 via Dl/DO 22, a clear signal is applied from the CPU to clear terminal CLR of latch 68. , latch 68 is cleared or reset, and the Q output goes high, allowing data line 58 to return to its high state. This high level state is detected by the keyboard detection data line 57,
The next scan code frame is the interface circuit 28.
This makes it possible for the data to be transmitted to

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a data processing device incorporating an interface circuit according to the present invention, FIG. 2 is a logic block diagram showing a specific example of the interface circuit according to the present invention, and FIG. FIG. 4 is a timing diagram of the operation of the interface circuit. 10...System bus line, 28...Keyboard interface circuit, 40...Keyboard, 52...Clock line, 58...
・Data line, 62... Encoder, 68...
···latch.

Claims (1)

[Claims] 1 a system bus for transferring addresses, data and control signals between a central processing unit, a storage device and a self-scanning serial keyboard, the keyboard having a clock line for carrying a keyboard clock output signal and a predetermined line for indicating key positions; a data line for transmitting a serially scanned output code in a frame with a start bit in the first position followed by a number of serial data bits;
an interface circuit for performing bidirectional communication between the bus bar and the keyboard, the interface circuit having a clock terminal connected to a clock line of the keyboard, a serial data input terminal connected to a data line of the keyboard, and a serial data input terminal connected to the bus bar; a number of parallel output data lines equal to the number of serial data bits connected, a number of stages equal to the number of bits in the frame, and a control line connected to the most significant stage; a serial-to-parallel shift register encoder that generates a control signal on the control line when the start bit and the predetermined number of serial data bits are stored in parallel under the control of a signal; and a central processing unit on the bus line. responsive to the keyboard clock output signal and the control signal to apply an interrupt signal to the data line and an inhibit signal to inhibit further transmission of data bits by the keyboard; - When bits are transferred from the encoder to the bus,
Another scan code from the keyboard to the encoder.
a control circuit responsive to a clear signal from the central processing unit to remove the inhibit signal from the data line to enable transmission of frames.