JPS605616A - Operational amplifier with high input impedance - Google Patents

Abstract

PURPOSE:To obtain an amplifier which suits to high-speed operation by providing a constant current supply circuit which supplies a current opposite in polarity and equal in absolute value to a base current and feeding it back to an input, and canceling a current flowing to the input terminal of an operational amplifier. CONSTITUTION:The constant current supply circuit 30 supplies the current opposite in polarity and equal in absolute value to the base current flowing from an inverted input terminal 9 when the voltage between operational amplifier input terminals is 0V. The collector of the PNP transistor(TR)40 of this circuit 30 is connected to the base of a TR13 to cancel the base current flowing from the inverted input terminal 9. Consequently, no charge flows out of a hold capacitor 6 and a droop phenomenon is eliminated. The current amounts of TRs 15 and 16 are constant regardless of the cancellation of the base current, so the operation speed never becomes slow.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an operational amplifier, and particularly to a high input impedance operational amplifier suitable for a hold circuit of a sample-and-hold circuit.

[Background of the invention]

FIG. 1 shows a block diagram of a conventionally commonly used sample and hold circuit.

In FIG. 1, the voltage follower buffer amplifier 2 has its non-inverting input connected to the signal input terminal 1 to be sampled and held, the inverting input and the output are short-circuited, and the output is connected via a resistor 3. and is connected to the analog switch 4.

One fixed contact α of this analog switch 4 is a high input impedance operational amplifier (hereinafter referred to as an operational amplifier).
A hold capacitor 6 is connected between this inverting input side and the output side of the operational amplifier 7. A resistor 5 is connected between the output side of the operational amplifier and the input side of the analog switch 4.

and the other fixed contact of the analog switch 4,
The inverting input side of the operational amplifier 7 is grounded, and the output side of the operational amplifier 7 is connected to the sample and hold output terminal 8.

Next, the operation of the sample hold circuit having the above configuration will be explained. Now, as shown in FIG. 1, when the analog switch 4 is connected to the contact α side by the control signal from the input terminal 1, that is, in the sampling mode, the buffer amplifier 2
The output of is e, the resistance value of resistor B is R8, and the resistance value of resistor 5 is R.

Assuming that the capacitance value of the hold capacitor B is C6 and R3=R5, the output of the operational amplifier 7 becomes -e with the time constant C0·R5.

Next, when the analog switch 4 is connected to the connection Ah side by a control signal from the input terminal 101, the hold mode is entered, and the output of the operational amplifier 7 is fixed at -eK.

However, at this time, if there is a leak in the analog switch 4 or if the input impedance of the operational amplifier 7 is not high enough, the charge in the hold capacitor 6 will be discharged, causing a so-called droop phenomenon in which the output amplitude gradually decreases.

In the sample bold circuit shown in Figure 1, the voltage across the analog switch 4 is always approximately OV, and leakage is unlikely to occur in this analog switch 4. The problem here is leakage of the hold capacitor 6 due to the input impedance of the operational amplifier 7.

FIG. 2 shows an example of a circuit using a general operational amplifier constructed of bipolar transistors as the operational amplifier 7 of FIG. 1. In FIG. Note that this figure shows the case of the hold mode.

In FIG. 2, the inverting input terminal 9 of the operational amplifier is connected to the pace of transistor 13, while its non-inverting input terminal 10 is connected to the pace of transistor 14.

8 is an output terminal, 11 is a positive power supply terminal, and 12 is a negative power supply terminal.

The voltage source 18, the transistor 17, and the resistor 19 constitute a constant current source circuit, and the transistors 15 and 16 form a first-stage differential transistor pair f:m.

These transistors 15, 16 form a Darlington circuit together with transistors 16 and 14, respectively, in order to increase the input impedance.

Note that transistors 20 to 26 and resistor 2 other than those described above
7 and the like are well known as general operational amplifiers, so their explanation will be omitted in the following explanation.

Now, if the current of the constant current source circuit is 1m, 4, and the current amplification factors of transistors 3, 14, and 15.16 are each 100, then the current flowing from the input terminal 9 to the pace of transistor 13 is = -X1m, (÷100÷100 = 50 nA.

Since this current is supplied by the charge held in the hold capacitor 6, the voltage across the hold capacitor 6 decreases over time, causing a droop phenomenon. To obtain a droop accuracy of 16 pits for a hold voltage of 5V, the allowable droop amount V is, and the capacitance of the hold capacitance 6 is 1000p7i',
If the hold time T is 20 μs, the allowable current is OV t=□=38n,A.

As described above, the means for reducing the current flowing from the input terminal 9 are (1) lowering the constant current amount of the differential transistor pair, and (2) reducing the amount of constant current of the differential transistor pair.
It is conceivable to add a further pressure Darlington transistor.

However, since either method degrades the response speed of the amplifier, it is impossible to implement this method with a sample-and-hold amplifier that requires high-speed operation.

Therefore, when a higher input impedance is required, it is common to use an operational amplifier whose first stage is an I'ET, which requires an extremely low gate current compared to the base current of a bipolar transistor.

However, in bipolar ICs, although it is possible to form FETs on the same chip, it complicates the process, increases costs, and speeds up the process.
, 'L professionals have the disadvantages of being subject to significant limitations.

[Purpose of the invention]

The present invention has been made to eliminate the above-mentioned drawbacks, and its object is to provide a high input impedance operational amplifier that can be constructed with bipolar transistors and is suitable for high-speed operation.

[Summary of the invention]

To achieve the above object, the present invention provides that the base current flowing to the operational amplifier input terminal has a closed loop gain of odB.
In the case of , it is the sum of the base current when the input is 0 and the base current corresponding to the base voltage change of 1 divided by the open-loop gain of the input voltage, and if the open-loop gain is large enough, the input is almost 00. Focusing on the fact that the base current is equal to the base current when [Embodiments of the Invention] The present invention will be described in detail below with reference to the drawings. Third
This figure is a circuit diagram showing an embodiment of the present invention, in which the same parts as in FIG. 2 are given the same reference numerals.

In FIG. 3, the constant current supply circuit 30 supplies a current that has the same absolute value and opposite polarity as the base current flowing from the inverting input terminal 9 when the voltage between the operational amplifier input terminals is 0. Note that, as is clear, this constant current supply circuit 30
Other than this, the circuit configuration is the same as that shown in FIG. 2 above.

As explained with respect to FIG. 1 above, the closed loop gain of the hold amplifier is 0 cLB. 2F,' As explained in relation to Figure 2, when the voltage between the input terminals of the operational amplifier is 0, the constant current of the first stage is 1 mA, and the transistor 1 is
If the current amplification factor of 3, 14, 15.16 is 100,
The base current flowing from input terminal 9 is 50 nA.

In the sample hold circuit shown in FIG. 1, when the output of the buffer amplifier 2 is eV, the operational amplifier 7 f: 47'
Base current change of the transistor forming J °ii', f
:calculate.

Assuming that e = i VR, = R, = 1 and Ω, the open loop gain of operational amplifier 7 is 8adB.
Then, the voltage at the output terminal 8 becomes -1V. Since the open loop gain is 80 dB, the inverting input terminal voltage of the operational amplifier is +100 μV.

Therefore, when ΔVBE = 100 μV, I+ΔI −=1.004, and when the first stage differential constant current amount is 1 mA, I=o, 5 mA, and ΔI=2 μA. Also, the current amplification factor of the first stage transistor is 100 x 100 nanometers, 2 μA, and the base current change f# = o2nA, which is 100
100 Ru.

This value is sufficiently smaller than the base current of 50 nA when the voltage between the input terminals of the operational amplifier is Or, so the Hesmi current flowing from the input terminal of the operational amplifier is always 50 nA.
It can be approximated as

Therefore, if the above-mentioned 50n'A is supplied to the operational amplifier input using the constant current supply circuit 3o of the embodiment of the present invention shown in FIG. It is possible to significantly increase the input impedance.

In Figure 3, within the IC, transistors 17 and 37
By making the resistors 19 and 39 the same size and pairing them, the constant current amount of the output of the transistor 17 and the output of the transistor 67 can be made equal.

Also, transistors 15, 16 and 35, 35, 13,
By pairing 14 and 33.34, the base current of transistor 13.14 and transistor 333
4 base currents can be made equal. When the base currents of the transistors 33 and 34 are supplied by the transistors 31 and 32, respectively, currents equal to the base currents of the transistors 33 and 54 flow through the diodes formed by the PIVP transistors 41 and 42, respectively.

For this reason, currents equal to the base currents of the transistors 33 and 34 are discharged from the collectors of the PNP transistor 40 paired with the PNP transistor 41 and the PNP transistor 43 which is paired with the PNP transistor 42, respectively.

Therefore, by connecting the collector of the PNI' transistor 40 to the base of the transistor 130, the base current flowing from the inverting input terminal 9 can be canceled. This prevents the charge from the hold capacitor 6 from flowing out, thereby making it possible to reduce the droop phenomenon.

In addition, the resistance 47 is 0 in principle, but if impedance occurs due to wiring resistance etc., it will become an offset voltage.
It functions to input the output of the transistor 43 to the pace of the transistor 14. Transistor 44. resistance 4
5. Voltage source 46 constitutes a bias circuit for transistors 31 and 32.

On the other hand, since the amount of current flowing through the transistors 15 and 16 is constant regardless of whether or not the base current is canceled, the operating speed will not be slowed down.

In principle, the example circuit shown in FIG. 3 can reduce the base current to the base current difference due to the input signal, but in reality, due to variations in the elements, this example circuit can reduce the input impedance f 1 oo times. It can be made higher.

〔Effect of the invention〕

As is clear from the above description, according to the present invention,
A current with the opposite polarity and the same absolute value as the base current flowing through the input terminal of the operational amplifier is fed back to the input to cancel the base current, so the input pace current of the operational amplifier composed of bipolar transistors can be reduced at the operating speed. A sampled bold circuit with less droop phenomenon can be realized using a lossless IC, and a sampled bold circuit can also be built into high-speed analog-digital and digital-to-analog conversion ICs.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional general sample and hold circuit, FIG. 2 is a circuit diagram using a conventional operational amplifier as a bold amplifier, and FIG. 6 is a circuit diagram showing an embodiment of the present invention. 6...Hold capacity 7...
......Operational amplifier 30......Constant current supply circuit isolation 9 Fig. 2

Claims (1)

[Claims] 1. A constant current source circuit comprising a transistor pair in which the base of one transistor is connected to an inverting input terminal and the base of the other transistor is connected to a non-inverting input terminal, and the emitter of the differential transistor pair. and a hold capacitor connected between the inverting input terminal and the output terminal, the operational amplifier generates a current having an opposite polarity and equivalent to a base current flowing through the base of the transistor connected to the inverting input terminal. 1. A high input impedance operational amplifier, comprising a constant current supply circuit, and an output side of the constant current supply circuit connected to the inverting input terminal. 2. A constant current supply circuit that generates a current with opposite polarity and equivalent to the base current flowing through the input terminal includes a second differential transistor pair equivalent to the first stage differential transistor pair of the operational amplifier, and the second differential transistor pair. a driver transistor that supplies the base current of the differential transistor pair; a diode connected to the collector of the driver transistor and having a conductivity type opposite to that of the driver transistor; and a diode connected to the cathode of the diode and having the same conductivity type as the diode. The high input impedance operational amplifier according to claim 1, characterized in that it is constituted by a current output transistor whose collector terminal is a constant current output terminal.