JPS6058652A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain the titled device which exhibits the effect of static protection always constant by a method wherein a region of reverse conductivity type is formed in a semiconductor substrate of one conductivity type, a region of one conductivity type being provided therein, and a metallized layer serving as an input-output terminal being then adhered thereon via insulation film. CONSTITUTION:An N type region 2 is epitaxially grown in the surface layer part of the P type semiconductor substrate 1, a P type region 3 being diffusion- formed therein, and all of the exposed surfaces of the substrate 1 and the regions 2 and 3 being then covered with an oxide film 4. By corresponding to the region 3, the input-output terminal 5 composed of a metallized layer of the same area as that thereof is formed on the film 4. Adoption of such a structure to transistors causes the emitter-collector voltage to become larger than the cathod- anode voltage, when a voltage due to static electricity is impressed on the terminal 5. However, since the reverse withstand voltage is through as equal to the collector-base reverse withstand voltage, the emitter-collector withstand voltage becomes smaller than the reverse withstand voltage, and the absorption of surge currents increases by combination with the difference in impressed voltages due to capacitance difference.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit having an electrostatic protection element.

(2) Description of the Prior Art As a means to prevent circuit elements from being destroyed by static electricity, it has been conventional to use diodes, transistors, resistors, etc. as protective elements. However, such a protection element requires a sufficiently large area in order to prevent destruction of the element itself, which is a factor in increasing the chip area. Furthermore, these protective elements have the disadvantage that their effectiveness varies depending on where they are placed.

(3) Purpose of the Invention The purpose of the present invention is to eliminate the above drawbacks and provide a semiconductor integrated circuit device that can be expected to have a constant electrostatic protection effect without increasing the chip area.

(4) Structure of the Invention The gist of the present invention to achieve the above object is to form a first semiconductor region of another conductivity type on one main surface of a semiconductor substrate of one conductivity type, and to form a first semiconductor region of a different conductivity type in this first semiconductor region. By forming a second semiconductor region of the same conductivity type, and providing an input/output terminal by a metallization process with an insulating film sandwiched over the second semiconductor region, an electrostatic protection effect can be provided to the input/output terminal itself. Can be done.

(5) Examples Next, embodiments of the present invention will be described using the drawings.

FIG. 1 is a sectional view of an input/output terminal section according to the present invention.

1 is a P-type semiconductor substrate, and 2 is an N-type semiconductor substrate formed in the substrate.
3 is a P-type diffusion region formed in the epitaxial region, 4 is an oxide film, and 5 is an input/output terminal.

On the other hand, Figure 2 is a cross-sectional view of a conventional input/output terminal.
Compared to the embodiments of the present invention, no P-type diffusion region is included.

The effects of the present invention will be described below by comparing FIG. 1 of the embodiment of the present invention and FIG. 2 of the conventional system. When considering the equivalent circuit between the input/output terminal and the substrate, the equivalent circuit in Figure 1 becomes as shown in Figure 3.T1 is a PNP transistor with the substrate as the collector, the N type epitaxial region as the base, and the P type diffusion region as the emitter. It is. C2 is the emitter-base junction capacitance,
C3 is the collector-base junction capacitance. Therefore, the capacitance between the emitter and the collector (substrate) of transistor T1 is: 2+63 and always 03
It will be a much smaller value. Further, C1 is the capacitance due to the oxide film between the input/output terminal and the emitter of T1.

On the other hand, the equivalent circuit of FIG. 2 is as shown in FIG. 4.

Dl is a diode with the substrate as an anode and the N-type epitaxial layer as a cathode, C5 is the junction capacitance of the diode, and C4 is the capacitance due to the oxide film between the input/output terminal and the cathode of Dl.

If the processes in FIG. 1 and FIG. 2 are the same except for the P-type diffusion region 3 in FIG. 1, the capacitance of 03 in FIG. 3 and the capacitance of 05 in FIG. The capacity between
The capacitance between the cathode of No. 1 and the substrate is also small. Also, since C1 in Figure 3 and C4 in Figure 4 are considered to have the same capacitance, when a voltage due to static electricity is applied to the input/output terminal, the voltage applied between the emitter and collector of T1 is equal to the voltage applied between the cathode and anode of Dl. Yoshi also grows bigger. Also, since the reverse breakdown voltage of D1 is considered to be the same as the reverse breakdown voltage between the collector and base of T1, the breakdown voltage between the emitter and collector of T1 is also smaller than the reverse breakdown voltage of Dl, and the difference in applied voltage due to the difference in capacitance mentioned above. Combined with this, the absorption of surge current by T1 is large.
If it brings about a large electrostatic withstand voltage effect, it becomes K.

(6) As described in detail of the invention, by providing a transistor under the input/output terminal, an increase in chip area can be prevented and a constant electrostatic withstand voltage effect can be obtained regardless of the element arrangement.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an embodiment of the present invention, FIG. 2 is a sectional view of a conventional system, and FIGS. 3 and 4 are equivalent circuits used to explain the present invention in detail. Figure 3 is the same as Figure 1 and Figure 4.
The figure is the equivalent circuit of Figure 2. In the figure, 1...P-type semiconductor substrate, 2...
...N-type epitaxial region, 3...P
4... an oxide film, and 5... a submission terminal. Figure 1 Figure 3 Figure 2 Figure 4

Claims (1)

[Claims] A first semiconductor region of an opposite conductivity type is formed on one principal surface of a semiconductor substrate of one conductivity type, a second semiconductor region of one conductivity type is formed within the semiconductor region, and an insulating film is formed on the second semiconductor region. A semiconductor integrated circuit device characterized in that input/output terminals are provided with metalized layers sandwiched therebetween.