JPS6058719A - Method for detecting pulse train - Google Patents

Abstract

PURPOSE:To detect all pulse trains with an identical program by presetting a prescribed value to a counter at a change point of a pulse, storing data in a storage means and reading the said data when the counter counts a specified time to improve the rate of recognition. CONSTITUTION:A detecting means 1 detects the leading edge of a synchronism bit pulse P1, an N value setting means 2 presets a numeral N to a counter 4 and operates a timer having a time T. On the other hand, a storage means 3 inputs the synchronism bit pulse P1 to store data ''1''. Figure (c) shows the content of storage. When a time T is elapsed after the leading (time t0) of the synchronism bit pulse P1, an output means 5 outputs a data ''1'' of the storage means 3 as detected data, resets the storage means 3 and presets a data ''0''. The means 2 presets the numeral N again based on the output of the counter and operates the counter 4 (t1). Since a data pulse D0 is risen before the time T is elapsed (t2), the similar operation to above is performed. Then the variance of the period is absorbed by deciding properly the time T to the period of the pulse.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a pulse train detection method for detecting a pulse train representing data such as time or index recorded on a tape in a tape recorder or the like.

(B) Prior Art In recent years, answering machines, dictating machines, etc. record the date and time of recording, as well as an index of the contents, and read out and display the data during playback. functions have been implemented.

The data recorded on the tape is as shown in Figure 1.
Start bit pulses 81 to S, synchronous bit pulses P, , P, , P, . . . , and synchronous bit pulses Ps.
, Ps . . . -D3, D4 to D, and during playback, eight start bit pulses S
, -S, it is recognized that the next pulse contains data, and the data between the synchronous bit pulses p, , p, , P, . . . is read.

Conventionally, when detecting the pulse train shown in FIG. 1, the rising and falling edges of the start bit pulses S, -S8 are detected using a sampling period that is approximately 1/10 of the pulse period of the start bit pulses S, -S. After detecting eight start bit pulses S, .about.S, the rising edge of the synchronization bit pulse P1 is detected. Then, as shown in FIG. 2, when the rising edge of the synchronous bit pulse P is detected, the pulse period T is reached. +7) Start the I/4 timer, and when that timer counts up, start a timer equal to the pulse period To. And period T. Every time the timer counts up, the pulse train signal is read and data D0-D,
Get V.

However, when playing back a tape, there is a variation in tape speed of about ±6%, which makes it impossible to read the tape completely, resulting in a lower recognition rate. For example, if the frequency of the pulse train is 16Hz, the pulse period is T. is 62.
5ms, and at this time, the variation range of the pulse period is 5ms.
8.8ms≦To≦66.3ms. On the other hand, the second
The tolerance range for the method shown in the figure is the period T. When the timer counts up for the fourth time, data D,
Since this is the range in which pulses exist, 59.0ms≦T
.

≦66.4ms. Therefore, since the lower limit of the variation range is lower than the lower limit of the allowable error range, the recognition rate decreases.

Furthermore, a method of detecting start bit pulses S, to S8 and data bit pulse D. - Since the detection methods for D8 and D4 to D7 are different, when trying to detect these pulse trains with a microcomputer, the programs for detection are different for each, so the program has the disadvantage that it is complicated and difficult to create. ing.

(/υ Purpose of the Invention The present invention has been made in view of the above-mentioned points, and provides a pulse train detection method that improves the recognition rate and can detect all pulse trains with the same program.

B) Structure of the Invention The present invention provides a pulse train detection method for detecting a pulse train in which a predetermined data pulse exists between synchronized bit pulses, in which a predetermined value N is preset in a counter means at the rising or falling edge of a pulse of the pulse train. At the same time, the operation of storing the data indicated by the pulse in the storage means, and when the counter means counts the time specified by the predetermined value N, outputting the data stored in the storage means as detected data, Further, it is configured to perform an operation of resetting the storage means and again presetting the predetermined value N in the counter means.

(e) Embodiment FIG. 3 is a block diagram showing an embodiment of the present invention. The rise detection means (1) inputs the pulse train reproduced from the tape and detects that the signal of the pulse train rises from 60" to 1". Based on this detection, the N value setting means (1) 2) and storage means (3). The N value setting means (2) presets a numerical value N in the counter (4) based on the outputs of the rising edge detection means (1) and the counter (4). Further, the storage means (3) receives the pulse train as an input, and the rise detection means (1)
The state of the signal of the pulse train, i.e., 1
'', and the stored data is reset by the output of the counter (4).On the other hand, the counter (4) to which the numerical value N is set by the N value setting means (2)
) performs subtraction counting using a predetermined clockfish, and obtains a predetermined time T by counting N clockfish, and outputs a signal 7 hours after the numerical value N is preset. Furthermore, even during the counting operation, the counter (4) is re-preset to the numerical value N by the N value setting means (2). The output of the counter (4) is applied to the data output means (5) and the N value setting means (2), and depending on the output after one hour has elapsed, the output means (5) is applied to the storage means (
3) while outputting the data stored in the storage means (
3) Reset. Further, the N value setting means (2) presets the numerical value N in the counter (4) again.

Next, the operation of the embodiment shown in FIG. 3 will be explained with reference to FIG. 4. For example, when detecting a pulse train such as the synchronization bit pulse P and data bit pulses D., D8, and D2 shown in FIG. Then, based on the detection output, the N value setting means (21 is a counter (4)
Preset the value N to , and operate the 1 hour timer. On the other hand, the storage means (3) inputs the synchronization bit pulse PI according to the detection output and stores the data ``1''. Here, FIG. 4(b) shows the timing of the timer operation of the counter (4), and FIG. 4(c) shows the stored contents of the storage means (3).

When one hour has elapsed since the rise of the synchronous bit pulse P (to timing), the output means (5) uses the output of the counter (4) to output the data 61'' stored in the storage means (3) as the pulse train detection data. At the same time, the storage means (3) is reset and data "0" is preset.At the same time, the N value setting means (2) is set to the counter (4).
) The numerical value N is preset in the counter (4) again based on the output from the counter (4), and the counter (4) is operated. (it timing) and the re-preset counter (4)
detects that one hour has elapsed, the data bit pulse D
. rises (at the timing of tt), the same operation as described above is performed, and the data bit pulse D is stored in the storage means (3). The data “1” is stored and the counter (4
) is preset to the numerical value N. Furthermore, when one hour has passed (timing of ts), data "1" in the storage means (3) is outputted from the output means (5) as a data bit pulse D. The counter (4) is preset to the value N.

On the other hand, when the data bit pulse D is 0'', the counter (4) that was preset at the timing t is not re-preset by the rising edge detection means (1) and is 1
Detect the passage of time. Then, after an hour, the counter (
4), the reset data "0" of the storage means (3) is outputted from the output means (5) as the data of the data bit pulse D.

By operating as described above, data represented by a pulse train is read, but as described above, the period of the pulse train varies within a range of ±6%. Therefore,
Consider the range in which malfunctions can be detected (consider the range in which malfunctions can be detected) in the time T created by the value N preset in the counter (4). As shown in Figure 5, when 1" pulses are continuous, the second pulse The timing of the rise must be within the re-preset time T, that is, the period indicated by A. Therefore, if the period of the pulse train is To, the possible range of the period T0 is T≦T0≦2T. Yes. On the other hand,
As shown in FIG. 6, when the pulses of 0'' are continuous, the data bit pulses D0~ between the synchronization bits P, , P,
D, is θ″, and in this case, the synchronization bit P
, the synchronization bit P must rise within the time T preset in the counter (4) for the sixth time, that is, within the period indicated by B. Therefore, the possible range of the period T0 of the pulse train is 5T≦5TO≦6T. Therefore,
The range of period T0 that satisfies both Figures 5 and 6 is T≦
T0≦100T.

Therefore, if the recording frequency of the pulse train is 16 Hzs, that is, the period is 62.5 ms, and the time T counted by the counter (4) is set to 57 m5, the period T of the pulse train. The allowable range is 57m5≦T0≦68.4ms
becomes. This is the range of variation in the pulse train, 58.8
It sufficiently allows ms≦To≦66.3ms,
Pulse trains can be detected reliably.

As described above, according to the embodiment shown in FIG. 3, when reproducing and detecting a pulse train containing data recorded on a tape,
Even if there is a variation of about ±6% in the pulse train, it can be detected accurately without malfunction.

On the other hand, the operation of the embodiment shown in FIG. 3 can also be performed using a microcomputer (hereinafter referred to as CPU). In this case, the pulse train signal reproduced from the tape is applied to the interrupt input terminal of the CPU. That is, an interrupt is generated at the rising edge of the pulse train. Further, it is desirable that the CPU has a timer interrupt function, and the timer interrupt is set to have a higher priority than the interrupt of the interrupt input terminal.

FIG. 7 is a flow diagram showing the operation of the CPU.

FIG. 7 (aJ is the interrupt processing routine INTI when the pulse train applied to the interrupt input terminal rises,
FIG. 7(b) shows an interrupt processing routine INTO when the timer counts up, and INTO is set at the higher interrupt priority level.

An interrupt is generated by the rising edge of the pulse train, and lNT
When the process 1 is executed, first, an internal flag FLG is set, and a timer provided inside the CPU is set to a time T.
The program presets the data N for creating , starts the operation of the timer, completes the interrupt processing of lNTl, and returns to the main program.

On the other hand, when the timer counts up, an interrupt is generated and INTO is executed. INTO first determines whether the flag FLG is set and sets the flag FLG.
If it is in the set state, "1" is stored in the RAM (random ACMOS memory) to accumulate pulse train data, and the flag FLG is reset. Also, flag F
If the LG is in the reset state, RAMK "0" is stored and data is accumulated. Then, data N for creating time T is preset in the timer again, the timer is started, and the process returns to the main program.

In this way, the pulse train is detected by executing the interrupt processing routine 1NTl by the rising edge of the H/+/S train, and further by executing the interrupt processing routine INTO by the interrupt of the timer, and the data of the sonopulse train is sent to the CPU. It is stored internally.

(F) Effects of the Invention As described above, according to the present invention, a pulse train with periodic variations can be reliably detected and recognized, and furthermore,
Since all pulse trains can be detected using the same detection method,
This has the advantage that it is easy to create programs for microcomputers, etc.

[Brief explanation of drawings]

Fig. 1 is a waveform diagram showing a pulse train, Fig. 2 is a diagram showing a conventional example, Fig. 3 is a block diagram showing an embodiment of the present invention, and Fig. 4 shows the operation of the embodiment shown in Fig. 3. A timing diagram showing,
5 and 6 are timing diagrams explaining the permissible range of the period of the pulse train, and FIGS. 7(a) and 7(bl) are flow diagrams when operating with a micro combiator. (1)... Rise Detection means, (2)...N value setting means, (3)...Storage means, (4)...Counter, (5)...Data output means. Fig. 1 Fig. 3 Fig. 7 (a) (b)

Claims (1)

[Claims] 1. In a pulse train detection method for detecting a pulse train in which a predetermined data pulse exists between synchronous bit pulses, a predetermined value N is preset in a counter means at the rising or falling edge of a pulse of the pulse train, and the predetermined value N is indicated by the pulse. an operation of storing data in a storage means, and when the counter means counts a time defined by a predetermined value N, outputting the data stored in the storage means as detection data, and resetting the storage means; A pulse train detection method for detecting a pulse train by again performing an operation of presetting the predetermined value N in the counter means.