JPS6058736A - Synchronizm control system - Google Patents

Abstract

PURPOSE:To prevent abnormal synchronism from being established by allowing a clock width supervising circuit to supervise a clock width of a transmission/ reception clock, and deciding it as synchronism abnormal until a normal clock is received over regulated time if an abnormal clock width different from the regulated time width is detected. CONSTITUTION:A comparator circuit 23 decides whether the clock width is <=90% or not. When the clock width is >=110%, a report signal is transmitted on a signal line 24 and when the width is <=90%, the report signal is transmitted to a signal line 25. When it is significant that the width is >=110% or <=90%, a signal representing abnormity is held in a clock abnormity holding circuit 26 in the timing of a clock signal CP1, and the abnormity of synchronism is reported by a signal on a signal line 27. If the abnormal clock is not detected within the regulated time, a reset signal is outputted to a signal line from a timer 28 to reset the clock abnormity holding circuit 26 thereby informing that the establishment of synchronism is possible.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization control method in a time division multiplex communication device.

Conventionally, as a synchronization control method for this type of time division multiplex communication device, a method has been adopted in which synchronization control is performed by monitoring a synchronization pattern and detecting clock disconnection of a transmitter/receiver. However, if there are multiple time division multiplex communication devices of the same type,
If these devices are installed on the same route and a frequency multiplexing device is shared in the time division multiplex high-speed line for these devices, the following problem arises. In other words, when one of a pair of time division multiplex communication devices experiences a loss of radio waves due to a power cut,
A time division multiplexed high speed line signal from a time division multiplex communication device forming a normal pair may pass through the frequency multiplexing device to a high speed line forming a pair with a time division multiplex communication device whose power has been cut off. Therefore, the time division multiplex communication device that is paired with the abnormal time division multiplex communication device and is being supplied with power should originally detect the synchronization abnormality and enter the synchronization abnormal state. However, in reality, synchronization may or may not be established, and synchronization is repeated at unspecified intervals to transfer high-speed line signals compatible with different time division multiplex communication devices to the corresponding time division multiplex communication device. The problem was that it was transmitted over a low-speed line accommodated by the network.

The purpose of the present invention is to monitor the clock width of the transmitting/receiving clock as a synchronization signal by focusing on the fact that the clock pulse width of the transmitter/receiver becomes abnormal when the above-mentioned abnormal mode is recognized in the time division multiplex communication device. It is an object of the present invention to provide a synchronization control method for a time division multiplex communication device that eliminates the above drawbacks by providing a circuit, prevents the establishment of abnormal table synchronization, and can operate stably.

The synchronous control system according to the present invention is realized by including a plurality of low-speed terminal lines, a plurality of time-division multiplex communication devices, a plurality of modulation/demodulation devices, and a common high-speed line. The plurality of low-speed terminal lines are for transferring low-speed terminal information. A plurality of time division multiplex communication devices are connected to a plurality of low-speed terminal lines, include a synchronization control section, and are used to perform time division multiplex communication. Each of the plurality of modulation and demodulation devices is connected to a plurality of time division multiplex communication devices to perform modulation and demodulation. The common high-speed line is connected to a plurality of modems and is used to perform time division multiplex communication.

In the present invention, the synchronization control unit provided in each of the plurality of time division multiplex communication devices for the common high-speed line includes a synchronization pattern detection circuit, a transmission/reception clock disconnection detection circuit, and a clock width monitoring circuit. ing. The synchronization pattern detection circuit is for establishing synchronization, and the transmission/reception clock disconnection detection circuit is for detecting disconnection of the transmission/reception clock from each modulation/demodulation device. The clock width monitoring circuit monitors the clock width of the transmitting/receiving clock, and if an abnormality or lock width different from the specified time width is detected, a clock width monitoring circuit monitors the clock width of the transmitting/receiving clock. It is something.

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a system configuration diagram of an embodiment of a time division multiplexing apparatus configured to apply the present invention. In FIG. 1, 101.102.201°202 are the first to fourth time division multiplex communication devices, 103°104.203.204 are the first to fourth modulation/demodulation devices, and 105°205 is the first and a second frequency multiplexing carrier, 106, 107, 206
, 207 is an individual high-speed line, 108 is a common high-speed line, 10
9.110 and 209.210 are synchronization control units. between the first and third time division multiplex communication devices 101.201 and the second and fourth time division multiplex communication devices 102;
．． 202 are coupled to each other, and the synchronization control units 110 .
210 and a terminal such as an exchange (IA not shown), as well as between the synchronization control unit 111, 211 and a terminal such as an exchange (IA)
(not shown) are communicated via low-speed lines 112, 212 and 113, 213. At this time,
If the power to the modem 204 is cut off or a disconnection occurs in the individual high-speed line 207, the modem 2
04 to the modulator/demodulator 104 disappears, and the time-division multiplexed high-speed signal from the modulator/demodulator 203 to the modulator/demodulator 103 goes around the individual high-speed line 107 toward the modulator/demodulator 04 inside the frequency multiplex carrier device 105.205. Time division multiplexers 101, 201, 102.2
Since time division multiplexer 02 has the same control method, time division multiplexer 1
At 02, abnormal synchronization is established, and the signals on the signal lines 211 and 212 are not only transmitted to the normal signal lines 111 and 112, but also the signal lines 113 and 114 K are abnormally transmitted.

At this time, since the signal from the individual high-speed line 107 is at a weak level, the clock width of the transmitter/receiver of the signal sent from the modulation/demodulation device 104 to the synchronization control section 110 often fluctuates.

FIG. 2 is a block diagram showing an embodiment for realizing the synchronous control method according to the present invention, and FIG. 3 is a diagram showing the operation of the circuit shown in FIG. 2.

The block diagram shown in FIG. 2 shows an example of a transmitting/receiving clock width monitoring circuit for performing synchronous control. In FIG. 2, for convenience, it is assumed that the clock width is normal if it is in the range of 90% to 110%, and the explanation will be made according to the timing diagram shown in FIG. 3.

Counter 20 for counting the clock width of transmission and reception
is counted up by the clock signal OLK. When the clock width is 110% or more, the detection circuit 21 for detecting the 110% clock width sends out the value of 110% to the load terminal LK, and the counter 20 holds this value. The counter 20 is reset by the transmission/reception differential signal 0ROK, and also has the function of setting the contents of the registers 221 and 222. Therefore, the comparison circuit 23
It is possible to determine whether it is 90% or less. A report signal is sent out on the signal line 24 when it shows 110% or more, and a report signal is sent out on the signal line 25 when it shows 90% or less. If 110% or more or 90% or less is significant, the signal representing the abnormality is held in the clock abnormality holding circuit 26 at the timing of the clock signal OPI.

A signal on signal line 27 reports a synchronization abnormality.

At this time, at the same time, the timer 28, which detects that a normal transmitting/receiving clock has been received by the clock signal OP1 for a predetermined time or more, is set to an initial state. Note that RT in FIGS. 2 and 3 is a signal indicating the distinction between transmission and reception in the timer 28.

The timer 28 is counted up by transmission and reception, but if an abnormal clock is not detected within the actual time, a reset signal is sent to the timer 28 on the signal line 29.
The clock abnormality holding circuit 26 is reset to notify that synchronization can be established. Note that this one circuit is one embodiment of the present invention, and it can be easily assumed that it can be realized by other circuits.

As explained above, the present invention detects an abnormal lock width to avoid establishment of incorrect synchronization due to the looping of other time division multiplexing signals, This has the effect of preventing erroneous information from being sent to low-speed terminals housed in the network and switching equipment. In particular, when connecting an exchange, the load on the exchange becomes excessive due to erroneous information, so the effects of the present invention are significant.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a time division multiplexing apparatus for implementing the synchronous control method according to the present invention. FIG. 2 is a block diagram showing an embodiment of a transmitting/receiving clock width monitoring circuit for realizing the synchronous control method according to the present invention. FIG. 3 is a timing diagram of signal waveforms showing the operation of the clock width monitoring circuit shown in FIG. 2. 101.201, 102.202... Time division multiplex communication device 103.203.104, 204... Modulation/demodulation device 105.205... Frequency multiplexing carrier device 106.20
6,107.207...Individual high speed line 8-108...Common high speed line 109.209,110.210...Synchronization control unit 11
1.211.112, 212, 113, 213, 114
, 214-...Low-speed terminal line 20...Counter 21...Detection circuit 221, 2
22...Register 23...Comparison circuit 26...Holding circuit 28...Timer 24.25, 27.29...
・Signal line patent applicant: NEC Corporation Representative, Patent attorney: Hisashi Inoro

Claims (1)

[Claims] a plurality of low-speed terminal lines for transferring low-speed terminal information; a plurality of time-division multiplex communication devices connected to the plurality of low-speed terminal lines and including a synchronization control unit and performing time-division multiplex communication; a plurality of modulation and demodulation devices each connected to the plurality of time division multiplex communication devices for performing modulation and demodulation;
a common high-speed line connected to the plurality of modems and for performing time-division multiplex communication, and provided in each of the plurality of time-division multiplex communication apparatuses for the common high-speed line. The synchronization control unit includes a synchronization pattern detection circuit for establishing synchronization, a transmission/reception clock disconnection detection circuit for detecting disconnection of transmission/reception clocks from each of the plurality of modulation/demodulators, and a clock interval of the transmission/reception clocks. and a clock width monitoring circuit for determining a synchronization abnormality until a normal or lock is received for a specified time or more if an abnormality or lock width different from a specified time width is detected. A synchronous control method featuring: