JPS6058743A - Serial bus interface - Google Patents

Abstract

PURPOSE:To obtain a bus.interface eliminating an address coincidence discriminating circuit, a timing circuit and a gate circuit by forming buses in serial and also not transmitting address information. CONSTITUTION:A bus controller 4 synchronizes an output data signal 22 to a clock signal 20 and outputs the result. A shift register group 50 is connected serially the same as that at the input side and shifted sequentially by the clock signal 20. When a data is shifted to a shift register 50 placed remotest from the bus controller 4, a set signal 24 is outputted. A value of each shift register 50 is stored in a register 51 of each process output device 3 by using the set signal. In order to ensure the reliability of data, a parity bit is transferred by including a transfer data, and parity check 55 is executed in storing the data to the register 51, the data is suppressed by an AND gate 56 and not stored at error detection. The processing above is performed cyclicly.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a CPU (central processing unit) of a computer and a PIlo
The present invention relates to a serial interface suitable for data transfer between (process input/output devices).

[Background of the invention]

The prior art is shown in FIGS. 1 and 2. Conventionally, in the range of several units, the CPU and PIlo are connected by a bus (FIG. 1). In other words, there is a CPU, a process input device 2, and a process output device 3 hardware.
These are connected by an address bus 10, a bidirectional data bus 11, and a control bus 12.

An example of the circuit of the interface section of each PI 10 is shown in FIG.

This circuit is used to capture data sent from the CPU via the address bus 10, data bus 11, and control bus 12 into the register 42. address bus 10
The upper address and setting address bus 27 are the outputs of the address setting circuit 45 (usually set by a group of small switches).
Both are input to the address discrimination circuit 40.

The address discrimination circuit 40 compares the data of both persons.
When the two match, an address match signal 28 is output.

Based on the control bus 12 signal and address match signal 28, the control circuit 41 detects the timing of receiving data on the output data bus, and outputs a gate control signal 25 and a set signal 26. In response to these signals, gate 43 is opened and data is loaded into register 42.

Thereafter, it is output to the process via the output circuit 44.

As shown in this example, the address match determination function.

A timing control circuit that performs complex timing control and a gate circuit that separates the pass line from the process input device are required. These circuits are provided for each PI 10, causing an increase in the number of parts and signal lines.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a bus interface in which an address matching circuit, a timing circuit, and a gate circuit can be removed by serializing the bus and not transmitting address information.

[Summary of the invention]

The present invention serializes the bus using the shift function,
PIlo implementation information is automatically collected, and based on the collection results, data is taken in and sent out cyclically in a minimum amount of time, efficiently, and while improving reliability.

[Embodiments of the invention]

An embodiment of the invention is shown in FIGS. 3-5.

Compared to the conventional example, the CPUI and process input/output devices 2 and 3
A bus controller 4 is inserted between the two. The bus controller 4 and the process input/output devices 2 and 30 are connected by a serial bus, and the interface section of each process input/output device 2 and 3 is constituted by a shift register 50.

The process input/output devices 2 and 3 will be explained with reference to FIG. 3, and the bus controller 4 will be explained with reference to FIGS. 4 and 5.

First, the process input device 2 will be explained. The bus interface signals include three signal lines: a clock signal 20 for shifting the shift register 5°, an input data signal 21 for transferring data from the process input device 2, and a set signal 23 for storing data in the shift register 50. It is.

First, the set signal 23 is output.

This signal is passed through the input circuit 52 to store information from the process in the shift register 50 (for the sake of simplicity, each process input device is assumed to have one byte of information. For those with multiple bytes, Similar processing can be achieved by simply connecting multiple shift registers in series.

).

In this state, the shift register 50 of each process input device 2
contains data to be transferred to the CPUI. To ensure data reliability, a parity bit generation circuit 54
Add a parity bit at . Thereafter, 20 sequences of clock signals are output, and since the shift registers 50 are serially connected, the data in the shift registers enters the bus controller 4 one after another.

When all bits have been shifted, all input information has been transferred to the bus controller 4.

Next, the set signal 23 is output again, and the above-mentioned process is repeated.

Next, the case of the process output device 3 will be explained.

In this case, the output data signal 22 is used instead of the input data signal, and the output set signal 24 and the same clock signal 20 as the input are used.

The bus controller 4 outputs the output data signal 22 in synchronization with the clock signal 20. Similar to the input side, the shift registers 50 are connected in series and are sequentially shifted by the clock signal 20.

When data is shifted from the hash controller 4 to the farthest shift register 50, a set signal 24 is output. By this signal υ, the value of each shift register 50 is stored in the register 51 of each process output device 3. In order to ensure the reliability of the data, a parity bit is included in the transferred data and a parity check 55 is performed when storing it in the register 51. When an error is detected, an AND gate 56
suppress it and do not store it. Since these processes are performed cyclically, when an error is detected, data updating is delayed by only one cycle.

Furthermore, it can of course be used without a parity circuit.

Next, the determination of plug-ins will be explained.

When starting up the system, it is necessary to determine the number and types of plug-ins installed. Therefore, how the plug-in detection 1 determination is performed between the process input device 2 and the bus controller 4 will be specifically described below.

The input data signal (outward path) 25 in FIG. 3 is connected to each process input device 2, and each process input device 2 has a final decision signal 28 for detecting the farthest plug-in. If there is a plug-in in the next stage, the final judgment signal 28 is 1
The tri-state gate 59 is closed and receives the shift signal from the plug-in (Fig. 3).
Process input device 2). In the case of the farthest plug-in, the pull-up resistor 100 is used, and the final judgment signal 28 is @H''
It is maintained at the level and connected to the input data signal (outward path) 25.

As described above, the signal from the bus controller 4 passes through the input data signal (outward path) 25, and the farthest tri-state gate 59% shift register 50° input data signal 21,
Shift register 50, input data signal 21.・・・・・・
, the shift register 50, and the bus controller 4 in a circular loop.

As a plug-in discrimination operation, a plug-in type code load signal 27 is output, and the data of the type code generation circuit 57 in each plug-in is set in the shift register 50 in accordance with this signal.

(The process input device 2 includes a multiplexer 58 for switching input data and type code.) The next operation is to store the recognition code in the bus control I:l-, 74 (7) 2-board memory 60 (Fig. 4). (a code different from the type code) and cancels the oscillation stop signal 28,
A clock signal 20 is output. This signal causes the data in the shift register 50 to complete one cycle, and it is determined that the data has completed one cycle by detecting the recognition code stored in the two-vote memory.

Through these operations, it is possible to collect the plug-in type codes of all plug-ins (9), and it is possible to determine the number and type of Lubra Gains installed.From this, the required number of transfer bits is calculated, and using this This enables efficient cyclic transfer.

On the other hand, regarding the process output device 3, the shift register 5
The process is essentially the same, just by shifting the data over 0 in the opposite direction. Between the process output device 3 and the bus controller 4, there is a bus controller 4 (FIG. 3), a shift register 50 . Output data signal 22. Shift register 50.・・・
A circular loop is formed including the shift register 1'50 (the farthest process output device 3), the right state gate 59, and the output data signal (return path) 26% bus controller 4.

FIG. 4 shows a detailed block diagram of the bus controller 4 for the process output device 3, and FIG. 5 shows a detailed block diagram of the bus controller 4 for the process input device 2.

First, FIG. 4 will be explained. The CPUI sets the number of data to be transferred in the register 65 (10) as an initial setting, and the bus controller performs a cyclic operation based on this value. That is, the oscillator 62 outputs the clock signal 20 at a constant frequency. Next, counter 6
3 measures nine clock signals corresponding to one byte (8 bits+1 parity) and outputs a storage signal 33 for every nine clock signals.

This signal counts down the counter 64 once and applies a load signal to the shift register 61. The kakunta value indicated by the 9-point counter 64 serves as the number of data to be transferred and the address signal 31 of the 2-vote memory 60.

The contents of the two-vote memory 60 indicated by the address signal 31 are stored in the shift register 61, and the stored data is transferred to the second process output device 3 by the clock signal 20.

After the counter 64 loads the value 32 of the register 65,
A countdown is performed, and when the count value reaches O, a set signal 24 is output.

This signal becomes the process output device 30 set signal and also resets the value of the register 65 to the counter 64 (11).

Cyclic transfer is performed as described above, but in order to ensure data reliability, the 2-board memory 60
When storing data, a parity bit 34 generated by a parity generation circuit 66 is added.

Next, the bus controller (FIG. 5) for the process input device 2 will be explained.

When data is stored in the 2-board memory 70, it is checked by the parity check circuit 72, and data is stored in the memory only when it is normal. However, due to the cyclic operation, if an error is detected, the data is stored in the memory for one cycle. It only slows down the storage of data.

Finally, the register 76 (FIG. 5) will be described.

Register 76 is plug-in type code control 1 oscillator 6
2 and the data for controlling the color 63 are transferred to the CPU.
Receive from I.

That is, the data to be taken in individually by the process input device and the process output device is stored in the register 76 according to the CPUI instruction (12), and the gate switching signal 29 is
Input data signal 21 or output data signal (return path) 26
By switching to , the type code from the input/output device is used.

Furthermore, when the oscillator 62 and the counter 63 receive the oscillation stop signal 28 from the CPUI via the register 76, they stop oscillating, and the counters enter a reset state.

〔Effect of the invention〕

According to the present invention, a serial bus is realized.

The number of bus signals can be greatly reduced, and the transmission of information at the same time is no longer necessary, making it possible to reduce the number of parts in process input/output devices and improve reliability.
This has the effect of efficiently sending and receiving data.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional embodiment, Fig. 2 is a circuit diagram of a conventional bus interface, Fig. 3 is a block diagram of an embodiment of the present invention, and Fig. 4 is a block diagram of an output path controller of the present invention. FIG. 5 shows a circuit diagram of the input system (13) bus controller of the present invention. 1...CPU, 2...Process entry method! , 3...
Process input/output device transfer signal % 21... Input data signal, 22... Output data signal % 23... Input set signal, 24.
... Output set signal, 25... Input data signal (outward path) %26... Output data signal (return path), 33...
Storage signal, 35...Data bus, 36...Address bus % 37...Number of data, 38...Parity check signal %39...Write signal, 50 River shift register, 59...Tri-state gate , 6Q...2-vote memory% 61...Shift register, 70...
2 boat memory, 71...Shift register% 73.
・・AND game), 74...(14) yzlIfl 12 Fig.

Claims (1)

[Claims] 1. In an interface connecting a central processing unit and an input device or an output device having a shift register,
a shift register for receiving the contents of the shift register of the input device or transmitting the contents to the shift register of the output device; A memory for exchanging data with the central processing unit, a counter for counting the number of data to be transferred based on an initial setting value from the central processing unit, and a memory for storing the clock signal and the contents of the shift register. A control circuit having an oscillator that generates a storage signal is provided, and the line control circuit has a one-loop circuit in which a shift register of the line control circuit and a shift register of the input device or the output device are connected in series;
A serial bus interface, characterized in that the data to be transferred is cyclically transferred independently of the central processing unit using the clock signal, the storage signal, and a set signal output from the counter. 2. In the serial bus interface according to claim 1, the input device or the output device is provided with a type code generation circuit that indicates the type of plug-in, and the type code is generated by the load signal from the control circuit. A serial bus interface characterized by storing data in a shift register of the input device or the output device.