JPS6059619B2 - Storage device distributed multiprocessor system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a system that takes into consideration the speeding up of parallel operation execution processing of multiprocessors, and more specifically, a system that takes into consideration the speeding up of parallel operation execution processing of multiprocessors. The present invention relates to a storage device distributed multiprocessor system characterized by a multiprocessor storage access method that can realize parallel operations.

In scientific and technical calculations, especially in simulator environments, simulator models are constructed using simultaneous linear equations, differential equations, and the like.

In the end, most of these types of problems involve repeated matrix calculations, which requires a large amount of calculation time on a general-purpose computer. When data can be handled as a matrix in this way, this data, that is, a vector, is suitable for handling in a system that can perform parallel operations. A vector is a set of mutually independent items (scalars), such as a set of row elements, a set of column elements, a set of diagonal elements, etc. of a matrix. In most cases, this vector is the unit of processing when calculating row examples. In vector operations, it is easy to utilize parallelism due to the independence of Raku items. Conventionally, as a system suitable for this type of vector calculation, a computer with a special architecture that has multiple arithmetic units inside a processor and can handle multiple pieces of data with a single instruction has been considered.

Although it has been optimized in terms of performance, its versatility has been limited and it has been considered as a dedicated vector computer. On the other hand, in a general-purpose multiprocessor system, vector operations can be divided among each central processing unit, but due to the overhead of the operation system or the execution capacity of each processor, even if ultra-high-speed central processing units are combined, the above-mentioned special Compared to arithmetic and arithmetic calculators, it had drawbacks such as lower performance.

An object of the present invention is to provide a storage device distributed multiprocessor system that has the advantages of the above two systems, particularly high speed and versatility.

In order to achieve the above object, the storage device distributed multiprocessor system according to the present invention includes a plurality of central processing units;
In a multiprocessor system comprising a main storage device and a switching control device that controls switching of data exchanged between each of the central processing units and the main storage device, each of the central processing units transfers the storage device access circuit to the internal storage device. The storage device access circuit controls whether to access the internal storage device in its own central processing unit or issue a data access request to the switching control unit according to the generated data address value, and Upon receiving a data access request from the processing unit, the switching control device performs data access control to the main storage device or an internal storage device in a central processing unit other than the source of the data access request according to the data address value. The access circuit of each storage device that receives a data access request from the storage device is configured to permit access to the internal storage device within the device itself.

According to the above configuration, the object of the present invention can be completely achieved.

The present invention provides a part of the main memory distributed in each central processing unit of a general-purpose multiprocessor system, and stores instructions/data handled by each central processing unit in its own storage (
By dividing the storage area so that the largest amount is distributed in the internal main storage (hereinafter referred to as the main storage within the device), multiple operations can be executed in parallel at high speed.

In particular, the purpose is to share a large amount of data distributed at regular intervals on a storage device among a plurality of central processing units to perform arithmetic operations. Internal storage is essentially different from conventionally known technologies such as buffer storage and scratchpad memory; it appears to be part of the main memory from the software, and is a partitioned section of the main memory. It is perceived as a territory. The in-device storage device of the present invention becomes more effective if it is implemented so that data can be read out at high speed in synchronization with the machine cycle of the device.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a system according to the present invention.

The multiprocessor system of the present invention includes a main storage device 1,
Memory switching control device 2, central processing units 30, 31, . . .
...3n1 internal storage device 40, 41...4n1
The storage device access circuit 80, 81, . . . 8n1 is composed of a first data line 5, a second data line 60, 61, . . . 6n, and an inter-device communication line 7.

FIG. 2 is a diagram showing an address format within the central processing unit.

In FIG. 2, 100 is the address format used when addressing the internal storage device, 102 is the internal storage display bit 101, central processing unit identification number, 103 is an address on the internal storage device, and 200 is the address for the main storage device. In the address format, 201 is a main memory display bit, and the number attached to the top of each address format indicates the bit. FIG. 3 is a diagram showing the entire main memory as seen from the program.

In FIG. 3, 300, 301, . . . 30n are areas of the internal storage device, and 400 is the main storage area. Below, the first
The operation will be explained using FIGS. Each central processing unit 30, 31, . . . 3n obtains a storage address 100 (or 200) from each storage device access circuit 80, 81, . . . 8n when executing an instruction. When this address indicates the internal storage device address format 100, check the central processing unit identification number 102 to determine whether the internal storage device of the own central processing unit should be accessed or whether the internal storage device of another device should be accessed. Decide whether to access it.

The central processing unit identification number 102 is an identification number uniquely given to each central processing unit in the multiprocessor system, and indicates that the internal storage device of the central processing unit that matches the identification number is to be accessed. show. The internal storage address 103 becomes the address of the target internal storage. Particularly in vector operations, the instructions and zeta handled by each central processing unit can be distributed so that they exist in the internal storage device of the own central processing unit in most cases, so the internal storage device address format 100 is When shown, the internal storage device within the own device can actually be accessed at high speed to realize high-speed arithmetic processing. In addition, when the central processing unit identification number 102 points to another central processing unit, the inter-device communication line 7 notifies the other central processing unit of this fact, interrupts the processing of that unit, and connects the second data line. 60
, 61, . . . 6n and the memory switching control device 2, it is possible to obtain data. memory address 100
(or 200) indicates the address format 200 on the main memory, the second data line 60, 61, 6n1
The memory switching control device 2 obtains instructions or data from the main memory device 1 through the first data line 5. This main memory access method is the same in concept as conventional main memory devices.
In vector operations, data for subsequent processing that cannot be stored in the internal storage device is stored in the main memory. Considering the special characteristics of vector data, the data on the main memory is overlaid in parallel on the free area of the internal storage in the central processing unit during arithmetic processing on the internal storage in the own device. By providing a means, high-speed processing is possible. In processing such as vector operations, what is the instruction? Since it often fits into a storage area of about the size of a word, it can be stored in the internal storage device of the device without using the main memory. In this embodiment, the internal storage device is used as an area for instruction words.
A total of 24K words, 16K'7-words, are prepared as a word operand area. The in-device storage device, like the buffer storage device, uses a faster storage element than the main storage device. For this reason, the processing on each central processing unit can draw out the execution ability corresponding to a 100% hit rate, whereas vector operations using a buffer storage device are difficult to execute with a high hit rate. Because everything is visible to the software, there is no need for complicated control means in the buffer storage device.Because it appears as a storage device that simply gives an address and reads data, the leakage time for access is small and the cycle time of the central processing unit is shortened. can be made smaller and improve performance. Furthermore, the architecture makes it easy for multiple central processing units to share and execute vector calculation processing, making it an optimal system for large-scale scientific calculation processing. Furthermore, since the in-device storage device of the present invention can be easily implemented on hardware so that the instruction word and data portion can be read independently, reading out instructions and reading out data can be performed in parallel.

As a result, further improvement in instruction execution time can be expected. As described above, the multiprocessor system of the present invention is optimal for large-scale scientific calculation processing, but also satisfies all functions as a general-purpose multiprocessor system.

As explained above, the present invention realizes a general-purpose high-speed multiprocessor system particularly suitable for large-scale scientific and technical calculations by configuring a multiprocessor system in which a part of the main memory is distributed and held within a central processing unit. I can do it.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the system of the present invention, FIG. 2 is a diagram showing the address format in the central processing unit,
FIG. 3 is a conceptual diagram of the storage space as seen from the software. 1...Main storage device, 2...Switching control device, 30, 31...3n...Central processing unit, 40, 41...4n... ...Internal storage device,
80, 81...8n...Storage device access circuit.

Claims (1)

[Claims] 1. In a multiprocessor system consisting of a plurality of central processing units, a main storage device, and a switching control device that controls switching of data exchanged between each of the central processing units and the main storage device, each of the central processing units It is equipped with a storage device access circuit and an internal storage device, and the storage device access circuit accesses data to the internal storage device in its own central processing unit or sends a data access request to the switching control device according to the generated data address value. The switching control device receives a data access request from each central processing unit and accesses the data to the main storage device or to the internal storage device of the central processing unit other than the data access request source according to the data address value. A storage device distributed multiprocessor characterized in that each storage device access circuit that performs control and receives a data access request from a switching control device is configured to permit access to a storage device within its own device. system.