JPS6059619U - automatic waveform equalizer - Google Patents
automatic waveform equalizerInfo
- Publication number
- JPS6059619U JPS6059619U JP15173583U JP15173583U JPS6059619U JP S6059619 U JPS6059619 U JP S6059619U JP 15173583 U JP15173583 U JP 15173583U JP 15173583 U JP15173583 U JP 15173583U JP S6059619 U JPS6059619 U JP S6059619U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- admittance
- control voltage
- self
- variable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Networks Using Active Elements (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の自動波形等化装置の構成図、第２図は第
１図に用いられていたＪＡＧＣ増幅回路部の構成図、第
３図は第２図に用いられていたＪｒＡＧＣ単位増幅回路
の具体的回路図、第４図は従来の自動波形等化装置の特
性曲線図、第５図は本考案に係る自動波形等化装置の構
成図、第６図は第５図に用いられている。／ＴＡＧＣ単
位増幅回路の具体的回路図、第７図は本考案に係る自動
波形等化装置の特性曲線図を示している。
図中、１は、／ＴＡＧＣ増幅回路部、２は擬似伝送路、
３はレベル検出回路、４は切替回路、５−１ないし５−
Ｎは、／ＴＡＧＣ単位増幅回路、６は検波回路、７は制
御電圧発生回路、８はトランジスタ、９は可変アドミッ
タンス回路、１０は可変容量ダイオード、１１は抵抗、
１２はコンデンサ、１３ないし１７は抵抗、１８．１９
はコンデンサ、２０−１ないし２０−Ｎは、／ＴＡＧＣ
単位増幅回路、２２は検波回路、２３は第１の制御電圧
発生回路、２４は第２の制御電圧発生回路、２５は第１
の可変アドミッタンス回路、２６は可変容量ダイオード
゛、２７は抵抗、２８はコンデンサ、２９は第２の可変
アドミッタンス回路、３０は可変ダイオード、３１は抵
抗、３２はコンデンサを表わしている。
第５図
２４
第６図Figure 1 is a configuration diagram of a conventional automatic waveform equalization device, Figure 2 is a configuration diagram of the JAGC amplifier circuit used in Figure 1, and Figure 3 is the JrAGC unit amplification used in Figure 2. A specific circuit diagram of the circuit, FIG. 4 is a characteristic curve diagram of a conventional automatic waveform equalization device, FIG. 5 is a configuration diagram of an automatic waveform equalization device according to the present invention, and FIG. 6 is a diagram used in FIG. ing. A specific circuit diagram of the /TAGC unit amplifier circuit, FIG. 7 shows a characteristic curve diagram of the automatic waveform equalizer according to the present invention. In the figure, 1 is a /TAGC amplifier circuit section, 2 is a pseudo transmission line,
3 is a level detection circuit, 4 is a switching circuit, 5-1 to 5-
N is a /TAGC unit amplifier circuit, 6 is a detection circuit, 7 is a control voltage generation circuit, 8 is a transistor, 9 is a variable admittance circuit, 10 is a variable capacitance diode, 11 is a resistor,
12 is a capacitor, 13 to 17 are resistors, 18.19
is a capacitor, 20-1 to 20-N is /TAGC
a unit amplifier circuit, 22 a detection circuit, 23 a first control voltage generation circuit, 24 a second control voltage generation circuit, 25 a first control voltage generation circuit;
26 is a variable capacitance diode, 27 is a resistor, 28 is a capacitor, 29 is a second variable admittance circuit, 30 is a variable diode, 31 is a resistor, and 32 is a capacitor. Figure 5 24 Figure 6
Claims (1)
が複数個縦続接続され、かつ、前記それぞれの増幅器が
、前記自己帰還回路に並列に接続された第１の可変アド
ミッタンス回路２５と、前記出力回路に番列に接続され
た第２の可変アドミッタンス回路２９とを備えてなる複
数個のＪ丁ＡＧＣ単位増幅回路２０−１〜２０−Ｎと；
該、／ＴＡＧＣ単位増幅回路２０−Ｎの出力信号を検波
する検波回路２２と；該検波回路の検波出力信号を受け
て前記第１の可変アドミッタンス回路のアドミッタンス
を変えるための第１の制御電圧を発生させる第１の制御
電圧発生回路２３と；該検波出力信号を受けて前記第２
の可変アドミッタンス回路のアドミッタンスを変えるた
めの第２の制御室、 圧を発生させる第２の制御電
圧発生回路２４とを備えた自動波形等化装置。a first variable admittance circuit 25 in which a plurality of self-feedback type amplifiers each having a self-feedback circuit and an output circuit are connected in cascade, and each of the amplifiers is connected in parallel to the self-feedback circuit; a plurality of J-cho AGC unit amplifier circuits 20-1 to 20-N comprising second variable admittance circuits 29 connected in series to the output circuit;
a detection circuit 22 for detecting the output signal of the /TAGC unit amplifier circuit 20-N; a first control voltage for changing the admittance of the first variable admittance circuit in response to the detection output signal of the detection circuit; a first control voltage generating circuit 23 for generating;
An automatic waveform equalizer comprising: a second control chamber for changing the admittance of a variable admittance circuit; and a second control voltage generation circuit 24 for generating pressure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15173583U JPS6059619U (en) | 1983-09-30 | 1983-09-30 | automatic waveform equalizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15173583U JPS6059619U (en) | 1983-09-30 | 1983-09-30 | automatic waveform equalizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6059619U true JPS6059619U (en) | 1985-04-25 |
| JPH021954Y2 JPH021954Y2 (en) | 1990-01-18 |
Family
ID=30336164
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15173583U Granted JPS6059619U (en) | 1983-09-30 | 1983-09-30 | automatic waveform equalizer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6059619U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS562719A (en) * | 1979-06-22 | 1981-01-13 | Nippon Telegr & Teleph Corp <Ntt> | f agc amplifying circuit |
-
1983
- 1983-09-30 JP JP15173583U patent/JPS6059619U/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS562719A (en) * | 1979-06-22 | 1981-01-13 | Nippon Telegr & Teleph Corp <Ntt> | f agc amplifying circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH021954Y2 (en) | 1990-01-18 |
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