JPS6059832B2 - Three-phase inverter load current disconnection - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for stopping the inverter by cutting off the current flowing through the main thyristor for supplying load power of a three-phase inverter by controlling the gate of the commutating auxiliary thyristor.

Conventional circuits of this type are constructed by combining all the firing signals of the thyristors at once and continuously applying the firing signals of the commutating auxiliary thyristor.

Therefore, even if the inverter stop signal obtained in connection with an abnormal condition such as a load short circuit is applied and the gate signal of the load-carrying thyristor is activated or disconnected, especially if the load power factor is lagging, the load current will be Without being cut off instantly,
continues until the commutation auxiliary thyristor corresponding to the main thyristor fires, i.e. up to 11
The time span was equivalent to three cycles. When such a delayed current flows to the load through the main thyristor, depending on the magnitude of the current, commutation energy may be insufficient and commutation failure may occur, resulting in unexpected accidents such as damage to the thyristor and burnout of the load. There was a risk that this would occur. It is an object of the present invention to provide a main thyristor by means of cutting off all the gate signals of the main thyristor and conducting the auxiliary thyristor for commutation of the main thyristor carrying the load current when the inverter stops the inverter and receives a cut-off signal. The purpose is to perform reliable commutation of the thyristor and reliably protect the main thyristor or load without causing overcurrent to flow.

The illustrated embodiment will be specifically described below.

Fig. 1 shows an auxiliary impulse commutation type inverter circuit for implementing the present invention, Fig. 2 is a circuit diagram showing an embodiment of the present invention, and Fig. 3 is a time diagram for explaining the operation of the present invention. It is a chart. First, in FIG. 1, E is a DC power source, which is obtained from an AC power source by the output of a converter including a thyristor. The thyristor 1 and the main thyristors 1 to 6 for carrying loads constitute one arm for one phase, and are connected to the DC power source E in the forward direction.

For the other two phases, thyristors 2 and 5 and thyristors 3 and 6 form a pair to form an arm, and the DC power supply E
connected to. 1A to 6A are commutation auxiliary thyristors,
Thyristors 1A, 4A1, thyristors 2A, 5A1, and thyristors 3A, 6A each constitute a thyristor arm, which is connected to the DC power source E in the forward direction.

C1 to C3 are commutation capacitors, L1 to L are commutation reactors, one for each phase is connected in series, and a second capacitor is connected between the thyristor connection points of each arm of the main thyristor and commutation auxiliary thyristor of each phase. Connect as shown in Figure 1. D1-D6 are feedback diodes, which are connected in antiparallel to the main thyristors 1-6, respectively. L is a load, which is connected to the thyristor connection point of each phase arm composed of main thyristors 1 to 6. Next, the gate control circuit shown in the second figure that applies to the main thyristors 1 to 6 and commutation auxiliary thyristors 1A to 6A will be explained with reference to FIG. do. Therefore, 12 signals are generated from the pulse splitter 8, and each of these signals is sent to each separate amplifier 1X to 6X1 and amplifier 1AX to 6A.
Each gate 1g of the main thyristor 1 to 6 respectively via X
6g and commutation auxiliary thyristors 1Ag to 6Ag. The signals applied to each of the gates 1g to 6g and 1Ag to 6Ag are as shown in FIG. 3, and such means are commonly used and well known to those skilled in the art. In addition, amplifiers 1X to 6X each have another input terminal 1y to 6y.
It has the effect of cutting off the output by the signal applied to (
Such an action can be easily performed by making the transistors conductive by signals applied to the input terminals 1y to 6y and setting the output level to O. ) Amplifier 1AX~
6AX is designed to also amplify the signals applied to each of the other input terminals 1Ay to 6Ay and supply them as output signals to the commutating auxiliary thyristors 1Ag to 6Ag (this functions as an OR gate). Reference numeral 9 denotes a signal generating device which detects an overcurrent caused by the rare short of the load L using, for example, a current transformer and generates a signal.

The signal from this signal generator 9 is transmitted to each amplifier 1X~
The signal is simultaneously supplied to each of the input terminals 1y to 6y of 6X, and is simultaneously applied to the pulse generator 10 to form a pulse. Reference numeral 11 denotes a logic circuit, which connects input terminals 1Ag to 6Ag of amplifiers 1AX to 6AX corresponding to thyristors 1A to 6A shown in FIG.
is configured to send a signal to

The configuration of such a logic circuit can be easily configured by receiving a signal from a pulse distributor and using, for example, the rising point of a gate signal applied to the main thyristors 1 to 6. In this way, the output signal of the logic circuit is transmitted to the amplifier 1A.
It is supplied to one of the input terminals 1Ay to 6Ay of X to 6AX corresponding to the thyristors 1A to 6A regulated by G in FIG. The specific configuration of this logic circuit 11 can be easily conceived by those skilled in the art based on FIG. 3, but for example, AND gates K1 to K6 shown in FIG.
Input terminals 1Ay to 6Ay of AX to 6Ax; output terminals 1G to 6 sent from the pulse distributor 8 to each amplifier 1x to 6x;
G and the pulse generator 10 with the connections shown. In the above configuration, the signals shown in FIG.
6g, 1Ag to 6Ag, three-phase AC power regulated to the frequency of each gate signal is supplied to the load L.

In the process in which three-phase AC power is being supplied to the load in this way, we will consider the case where the load occurs at current TO and the load current begins to rise rapidly. A signal is generated from the signal generator 9 at each input terminal 1 of the amplifiers 1X to 6X.
y to 6y, and thereby the gate signals of all the main thyristors 3, 4, and 5 which are firing at the time point b are cut off, and the gate signal of the main thyristors 3, 4, and 5 is However, when the auxiliary commutating thyristor 3A is ignited by a command from the logic circuit 11, the energy stored in the capacitor C3 applies a reverse bias to the main thyristor 3 due to the resonance effect, so that the main thyristor is forced to Be turned off. As a result, the load current is suddenly cut off, leaving no room for current to flow through the other main thyristors 4 and 5, which naturally turn off. Comparing this operation with a conventional load current disconnection circuit, in the conventional circuit, the gates of the main thyristors 3, 4, and 5 are only briefly disconnected at time TO, so there is no follow-on current, especially in the case of a delayed load. continues to flow through the main thyristors 3, 4, 5, and this phenomenon continues until the time t1 when the gate signal 3g of the thyristor 3 is supplied from the pulse distributor 8. Therefore, if the current increases abnormally due to the load's shortcut between time TO and time t1, even if the LC resonant circuit is closed at time t1, commutation energy will be insufficient and commutation will not be possible. It may lead to. This causes the load current to further increase, and there is a fear that the main thyristor or the load may become unable to reproduce. In this regard, in the circuit of the present invention, since the load current can be cut off instantaneously at time TO, there is no room for an abnormal increase in the load current, and damage to the main thyristor of the inverter and the load can be prevented. It should be noted that the commutation auxiliary thyristor, which is activated by the signal from the logic circuit 11 according to the time point when the signal is generated from the signal generator 9, is regulated as shown in FIG. 3G. A comrade arm short circuit cannot occur.

This means that the firing relationship between the two commutating auxiliary thyristors constituting one arm, for example thyristor 2A and thyristor 5A, is at least 600C (assuming one cycle of the inverter is 360°C), and the firing occurs first. This is clear from the fact that after the thyristor 2A or 5A which has been used has sufficiently recovered its blocking ability, the other thyristor 5A or 2A is fired. As described above, the load current disconnection circuit of the three-phase inverter according to the present invention sends a gate signal from the pulse distributor to the main thyristor and the commutation auxiliary thyristor, and supplies a signal in response to an abnormal condition such as load shortcut. In a circuit configured to cut off only the gate signal of the main thyristor by a signal from a signal generator, the circuit includes a pulse generator that pulses the signal from the signal generator and a signal from the pulse generator. A logic circuit is provided for regulating the commutating auxiliary thyristor, which provides a signal with a width of 60° C. within a range that prevents short-circuiting of the commutating auxiliary thyristor.

Based on this configuration, when an inverter stop signal is supplied from the signal generator, not only the main thyristor gate signal is cut off but also the commutation auxiliary thyristor is instantaneously ignited to ensure the power flowing through the main thyristor. It is possible to reliably prevent commutation failure due to an abnormal increase in load current when the load is short-circuited or the like. Furthermore, the logic circuit is configured to prevent arm short-circuiting of the commutating auxiliary thyristor when the inverter stop signal is supplied from the signal generator, so that the load current can be reliably controlled regardless of the inverter's operating frequency. You can make a decision.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an auxiliary impulse commutation type inverter, Fig. 2 is a circuit diagram showing an embodiment of the present invention, Fig. 3 is a time chart for explaining the operation, and Fig. 4 is a logic circuit diagram. . 1 to 6... Main thyristor, 1A to 6A...
... Commutation auxiliary thyristor, 7... Oscillator, 8
...Pulse/distribution amount, 9...Signal generation circuit, 10...Pulse generator, 11...
・Logic circuit.

Claims (1)

[Claims] 1 A three-phase bridge type inverter that sequentially sends a gate signal from a pulse distributor to a main thyristor and a commutation auxiliary thyristor, in which all of the thyristors are A pulse generator for converting the signal from the signal generator into a pulse, and a gate for the main thyristor from the signal from the pulse generator and the pulse distributor. It receives the signal and sequentially divides the time from the start of firing of one main thyristor to the start of firing of the main thyristor responsible for the next firing, and is connected to the + side and - side of the input power supply in each division. A commutating auxiliary thyristor corresponding to the conducting main thyristor in the thyristor group on the side where only one main thyristor is conducting among each of the three main thyristor groups is specified, and the commutation auxiliary thyristor corresponding to the conducting main thyristor in the thyristor group on the side where only one main thyristor is conducting in each group of three main thyristors is A three-phase inverter load current disconnection circuit comprising a logic circuit that operates only the gate circuit of a specified commutation auxiliary thyristor.