JPS6061987A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To ensure the extremely stable operation of a semiconductor memory with no use of a clock for drive by providong a latch circuit to an output buffer circuit. CONSTITUTION:It is supposed that the data of a flip-flop consisting of T1-T4 is defined as N1=H and N2=L respectively. Thus the final stage transistor T12 is off with a T13 turned on to on L level. Then data defined as D=H and D'=L are transmitted. Thus T15, T6, T7 and T8 are turned off, on, on and off respectively. In other words, N1=L and N2=H are satisfied and the data of a latch is inverted. With this inversion, the H level appears at an output. Then T5-T8 are all turned off in a precharge state, i.e., under the conditions D=D'=H. This gives no effect to the state of the flip-flop. Therefore this circuit holds the previous information unless the data changes. An OE is usually set at the L, and the H level is inpressed to attain the floating state of the output.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an output buffer circuit in an internally synchronous circuit type static RAM.

Conventionally, there have been circuits of this type as shown in FIGS. 1 to 8. In FIG. 1, the sense circuit output is passed through two stages of inverter circuits and inputted to a NAND gate and a NOR gate. NAN
The configuration is such that the D gate output is connected to the gate of the final stage P-channel transistor, and the output of the NOR gate is connected to the final stage N-channel gate.

C8 is the chip select signal that determines chip selection.
is an output enable signal for floating the output. Figure 2 shows the N-
An N-channel transistor is provided in parallel with the channel transistor, and data n and i5 are input to its gate. A control gate using a PC (precharge) signal is installed between the flip-flop output and Vcc/GND.One output is directly connected to the gate of the final stage P-channel transistor, and the other output is connected to the final stage N-channel transistor through an inverter circuit. −
This is a circuit configuration connected to the gate of a channel transistor.

Figure 8 shows the flip-flop data output as NOR or NA.
The circuit configuration is such that the signal is input to an ND gate, and through an inverter circuit, one input is input to the final stage P-channel transistor, and the other input is input to the N-channel transistor.

Before explaining the operation of the prior art, the internal synchronous circuit system will be briefly described.

Due to the circuit configuration of the CMOS static RAM, as shown in FIG. 4, DC current inevitably exists in the memory cells and the sense circuit portion, making it difficult to reduce power consumption using conventional circuit systems. However, a change in the address is detected and the synchronization signal (
By internally generating a clock (clock) and operating dynamically, it is possible to reduce power consumption.

That is, as shown in FIG. 5, the bit line pull-up transistor TPull is not pulled up all the time, but is charged only during one cycle time.

There is also a method in which the sense circuit operates only during the time it needs to operate. Here, PC means precharge and corresponds to the aforementioned clock. Figure 6 shows the ζ timing diagram.

Now, in such an edge sense circuit system, it is necessary to take into account that the address signal also reacts to noise. In other words, it is desirable that even if noise is added to the address signal, the output waveform will not be affected by it. This is because fluctuations in the output waveform due to noise make it unstable, and if data is transmitted at that timing, it may lead to malfunction of the system.

Now, the operation of the conventional circuit will be explained. In the Niji sense circuit system, when a clock is generated, the circuit enters a precharge state and both data D and b become SH level. Consider the state of the output at this time. First, in the circuit of Figure 1, C8-'H'
Therefore, the sense circuit output becomes 'L#. And the final stage P
-Channel transistor input is 'H' N-channel transistor input is 1H'. In other words, 1L# at the output
A level appears. In the case of the circuit shown in FIG. 2, since it is PC-L, the flip-flop output is at the 'IH# level. The gate of the final stage P-channel transistor is IH' and the gate of the N-channel transistor is 1L'. Therefore, both transistors are in the 5'off' state and the output is floating. In the case of the circuit shown in FIG. 8, the output of the flip-flop is at L# level, the input of the final stage P-channel transistor is 'L', and the input of the N-channel transistor is also at %L#. Therefore, an H level appears at the output.

As described above, in the conventional circuit, when noise is added to the address signal and a clock is generated, the output becomes 1H' or 1L# or a floating state, similar to a normal address change. This has the drawback that normal data is output after the conventional output data is inverted or in a floating state, resulting in an unstable output state.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and the purpose of this invention is to provide a device that operates extremely stably and does not require a drive clock by providing a latch circuit in the output buffer circuit. It is said that

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 7, it is composed of T1 to T4. Connect Ts=Ts in parallel to the flip-flop circuit. A latch configuration is used in which data D is input to TI, 5 inputs are connected to TI, inverted data s of 5 is inputted to T6, and inverted data of D is inputted to Ts. The circuit configuration is such that the output from the TI and T4 sides is input to the gate of the final stage P-channel transistor T12 through an inverter circuit, and the output from the TIT2 side is input to the gate of the final stage N-channel transistor TI3. In addition, a P-channel transistor T9 is installed in series on the Vce side of this circuit, and a P-channel transistor T9 is installed in parallel on the GND side.
The two N-channel transistors Tl0TII are control transistors for OE. First, the data of the flip-flop consisting of T1 to T4 is N, 1111
Assume that T″H# N2=%L#.The final stage transistor T12 is 1 OFF #T13 is 5ON', and the ``L# level is output.

Next, when D=1H'b=1L' data is transmitted, T'1
s is t off; T6 is 1 on; Ts is 1 off. That is, N, ts″IL#N2−′H#
As a result, the data in the latch is inverted. Due to this inversion, 1H level appears at the output. Next, in the precharge state, that is, under the condition of D=D-'H', Ts-Ts are all 1 off', and do not affect the state of the flip-flop. Therefore, this circuit is configured to continue holding previous information as long as the data does not change. Note that OE is normal, and if it is desired to make the output floating, it can be achieved by applying the H level.

A timing diagram is shown in FIG. In the conventional circuit, due to the precharge operation, the output first appears in a 1H# or 1L' or floating state, and then normal data appears. Therefore, if noise is added to the address and the edge sense circuit reacts and a precharge clock is generated, the output will behave in the same way as when the address changes, ``H'' or 1L.
Alternatively, the corresponding address data is output after entering the floating state. In this invention, when noise is added to an address, the edge sense circuit activates and performs a precharge operation, but as mentioned above, the state of the flip-flop does not change during precharge, and after precharge, the bit at the same address is selected. Therefore, the same data appears again in n, I5. Therefore, the output does not change.

In this way, in this invention, the output data does not change unless the input data to the output buffer changes, so the output changes even in response to address noise, and there is no need for a clock for the driver, resulting in stable output. Waveforms can be obtained.

In the above embodiment, the CMO8-RAM is shown, but if it is an internal synchronous circuit type, it can be used with other static RA.
M may also be used (the same effect as in the above embodiment is achieved).

As described above, according to the present invention, the circuit configuration is such that only the data corresponding to the address is directly output, so that it is possible to obtain a device that can operate stably.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a conventional output buffer in which the %L# level is temporarily output before normal data is output; Figure 2 is a circuit diagram of a conventional output buffer in which the output buffer is temporarily in a floating state; A conventional output puffer circuit diagram in which a temporary 1H# level is output, Figure 4 is a diagram showing a conventional memory column line, Figure 5 is a timing diagram of an internal synchronous circuit system, and Figure 6 is a timing diagram of an internal synchronous circuit system. 7 is an output buffer circuit diagram according to an embodiment of the present invention, and FIG. 8 is a timing diagram in comparison with a conventional one.The same reference numerals in each figure indicate the same or equivalent parts. Engraving of Tai Masuo's drawings (no changes in content) Figure 1 Figure 2 C Figure 3 - (( Figure 7 Figure 8 Procedural amendment (method) , Representative of the person making the amendment: Katayuni Nishibu 4, Agent - 1, - 5, Date of amendment order: January 81, 1981 (shipment date) 6. Subject of amendment (1) Application (2) Specification (3) Drawing 7, Contents of the amendments: Engravings of the application, specification, and drawings (no changes to the contents) Above procedural amendments (voluntary) 2. Title of the invention: Semiconductor memory device 3: Relationship with the case of the person making the amendments Patent Applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name
(601) Mitsubishi Electric Co., Ltd. Representative Katayuni 8th Department 4, Agent 5, column for detailed explanation of the invention and column for brief explanation of drawings of the specification subject to amendment. 6. Details of the amendment (1) The phrase "precharge" on page 8, line 14 of the middle cylinder of the specification is corrected to "precharge." (2) On page 8, line 18, the phrase ``also against noise, noise, etc.'' is corrected to ``the memory device is affected by noise, etc.''. (3) In the second line of page 4, the word "unstable" is corrected to "memory device is unstable." (4) On page 4, lines 5 to 6, the word "nijisense" is corrected to "edgesense." (5) In the fourth line of page 6, the phrase "this circuit" is corrected to "of this circuit." (6) On page 6, line 18, the text "rTIFI is" is corrected to "TIL is." (7) On page 8, line 17, the phrase "timing diagram" is corrected to "diagram showing memory column lines."

Claims (2)

[Claims] (1) A static RAM with an internal synchronous circuit system is characterized in that when the address changes, the output does not temporarily go into a floating state or a ゚H' or 1L level state, and the data corresponding to the address is directly output. Semiconductor memory device. (2) A latch circuit that does not require a driving clock is provided in the output buffer circuit, and the circuit configuration is such that the same data is latched until a data change is required. The semiconductor memory device described in Section 1.