JPS6063661A - Sharing method of hardware between microprocessors - Google Patents

Abstract

PURPOSE:To improve the operation rate of the whole device by allowing plural microprocessors to access the same hardware on time-division basis. CONSTITUTION:A microprocessor (MPU) 4 has priority over an MPU5, and they operated synchronously with the same clock signal. When the MPUs 4 and 5 access a Japanese character pattern generator 6 at the same time, their address decoding signals are detected by address decoding circuits 7 and 8. The input of a reset signal to an FF circuit 16 is cut off with the address decoding signal of the MPU4, and consequently the address decoding signal of the MPU5 is suppressed by a bus driving circuit 9. When the MPU4 finishes accessing the character pattern generator 6, the output of its address decoding signal is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for joint use of hardware by a plurality of microprocessors, which simultaneously accesses the same hardware connected to the plurality of microprocessors.

(b) Background of the technology In order for multiple microprocessors to access the same hardware simultaneously, a microprocessor with priority usage rights (hereinafter referred to as MPU) temporarily suspends other MPUs, and during this time When accessing the corresponding hardware, certain steps are taken to temporarily stop other MPUs. In addition, even after access to the relevant hardware is completed, other MPUs must take certain steps to release the temporary suspension again.
Unpause.

In devices where the same hardware is frequently accessed simultaneously by multiple microprocessors, the above steps are taken each time, which is disadvantageous in terms of operating efficiency, and it is difficult to put a more efficient shared usage method into practice. requested.

(C) Prior Art and Problems The prior art will be explained using a printer device as an example with reference to one drawing.

FIG. 1 shows a schematic diagram of a conventional printer device.

In the figure, 1 is a character information buffer section, 2 is a graphic information buffer section, 3 is a printer section, 4 is an MPLI for characters, 5 is an MPU for graphics, and 6 is a Japanese character pattern generator.

Furthermore, MPLI 4 for characters is M for controlling character information buffer section 1.
PU and MPU 5 for graphics represent MP[I for controlling the graphics information buffer section 3, respectively. Also, the Japanese character pattern generator 6 is a character MPU 4. It is assumed that it is shared by the graphic MPU 5. However, it is assumed that the priority right to use the Japanese character pattern generator 6 belongs to the character MPII 4.

If you are trying to create a manual containing 9 shapes in Japanese, you will need to use the information transferred from the main computer.

The explanatory text portion is taken out to the character information buffer section 1, and the graphic section (including the explanatory text within the figure) is taken out to the graphic information buffer section 3. For text! The IPU 4 accesses the Japanese character pattern generator 6, reads out three Japanese character patterns, and outputs them to the printer section 3 so that the information regarding the explanatory text can be processed by the printer section 3.

On the other hand, the MPU 5 for two figures accesses a dictionary related to figure processing (not shown) to create figures according to the input information, and accesses the Japanese character pattern generator 6 for Japanese sentences to be used in one figure. Although a Japanese sentence will be created, the priority usage right for the 2nd Japanese character pattern generator 6 is for the character M.
Since it is located in PU 4, it will be on standby so that it can be accessed while the Japanese character pattern generator 6 is being used in the 3-character liver υ4.

In order for the character MPtl 4 to access the Japanese character pattern generator 6, there is a procedure for accessing the Japanese character pattern generator 6, a procedure for temporarily suspending access from the graphic MPtl 5, and a time to access after the access is completed. You need to follow the steps in reverse. For this reason, there is a problem that the usage rate of Japanese in one figure is high (if the number of accesses to the one Japanese character pattern generator 6 is high, the operating efficiency will decrease).

(d) Purpose of the Invention The present invention aims to provide a novel method for jointly using hardware by a plurality of MPUs that eliminates the above-mentioned drawbacks, and in particular, it is an object of the present invention to provide a method for jointly using hardware by a plurality of MPUs. multiple MPs, which allocates hardware usage rights on a time-sharing basis and improves the operating efficiency of the entire device.
The objective is to realize a method for joint use of hardware by U.

(e) Structure of the Invention The present invention provides an apparatus comprising a plurality of microprocessors for controlling predetermined means, in which the plurality of microprocessors are used for information transfer via a line drive circuit that sends signals onto a common path. with a common road.

When the plurality of microprocessors simultaneously access the same hardware connected to the common path for address transfer, the entire device This can be achieved by a method of jointly using hardware using a plurality of MPLIs, which is characterized by making it possible to improve the operating efficiency of the MPLI.

(f) Examples of the invention The present invention will be explained below with reference to the drawings.

FIG. 2 is a block diagram of a printer device which is an embodiment of the device according to the present invention, and FIG. 3 is an operational diagram of FIG. 2.

In the figure, 7.8 is an address decoding circuit.

9.10 is a bus driver circuit, 11 is a frequency oscillation circuit,
12 is a timing generation circuit, 13 and 16 are flip-flop circuits (hereinafter abbreviated as F and F circuits), 14 is a NOT circuit, and 15 is an AND circuit.

Note that the same symbols as in FIG. 1 indicate the same contents. In addition, in Fig. 3, a, a', b, b', BE, C (C1 to C
4) , CL, T (Tl to T8) represent the respective signals in FIG. 2, and in FIG. 2, d and e represent common paths (hereinafter referred to as buses) for transferring data,
a is address decode signal of MPU4 a l is liver U4
The access time of the Japanese character pattern generator 6 by b
is the address decode signal of MPIJ5, b' is the MPU5
The access time of the Japanese character pattern generator 6 by
BE is a bus enable signal and is a signal obtained by ANDing an address decode signal and a clock signal C4.

CI, C2 are the output signals of the F, F circuit 13 and are the clock signals of the MPII 4; C3, C4 are the output signals of the F, F circuit 16, and are the clock signals of the MPU 5; CL is the output signal of the timing generation circuit 12, which is the reference clock signal; d is address bus.

e represents a data bus, T (Tl to T8) represents an output timing signal of the timing generation circuit 12, F and F1a represent output signals of the F and F circuits 13, and F and F16 represent output signals of the F and F circuits 16, respectively.

In this embodiment, MP[4,
MPII5. which controls the graphic information buffer unit 2. A Japanese character pattern generator that records Japanese character patterns6. The address decode signal a accessing the Japanese character pattern generator 6 of the MPU 4 is detected and the address bus d is
q output address decoding circuit 7. An address decode circuit 8 detects the address decode signal accessing the Japanese character pattern generator 6 of the MPU 5 and outputs it to the address bus d.The address decode circuit 8 detects the address decode signal that accesses the Japanese character pattern generator 6 of the MPU 5 and outputs it to the address bus d. A bus driver circuit 9.d is a drive circuit for sending the address decode signal taken out from the address decode circuit 8 onto the signal BE according to the AND condition. A bus driver circuit 10 which is a drive circuit for reducing the influence on the MPU 5 when transmitting and receiving information between the MPU 4 and the Japanese character pattern generator 6, and also for transmitting and receiving information between the MPU 5 and the Japanese character pattern generator 6. ．． Frequency oscillation circuit 11 that generates a reference frequency used in timing generation circuit 12, Frequency oscillation circuit 1
A timing generation circuit 12. generates a reference clock signal CL and a timing signal T (Tl to T8) based on the reference frequency from 12.1. Input the reference clock signal CL and timing signal TI from the timing generation circuit 12, ↑5, and input the MP
F, F to create clock signals CI and C2 for Ud
Circuit 13. a NOT circuit 14 that outputs a NOT signal of the address decode signal a to the AND circuit 15; An AND circuit 15 which ANDs the output signal of the NOT circuit 14 and the timing signal T5 and outputs the timing signal T5 to the F and F circuits 16 only when the AND conditions match. It is composed of F and F circuits 16 which input the reference clock signal CL and timing signals TI and T5 from the timing generation circuit 12 and generate clock signals C3 and C4 for the MPU 5.

In this embodiment, MPU4 is given priority over MPU5, and MPU4 and liver U5 operate synchronously using the same clock signal CL. Also F, F circuit 1
3.1G is sent by the timing signal TI and reset by the timing signal T5, and the F and F circuits 1 at this time
The output of 3.16 is the key point 4. MPU5 clock signal (
CI, C2, C3, C4).

The operation of this embodiment will be explained below, mainly referring to the operation diagram shown in FIG.

When the MPU 4 and the MPU 5 simultaneously access the Khonfu character pattern generator 6, the address decode circuits 7.8 detect the address decode signal a from the MPU 4 and the address decode signal S from the MPU 5, respectively. At this time, the input of the timing signal T5, which is a reset signal, to the F and F circuits 16 is stopped by the address decode signal a, so the clock signal C3, which is an output signal, continues to rise (as shown in FIG. 3). do. As a result, the address decode signal BE is suppressed by the bus drive circuit 9 because the signal BE which is ANDed with the clock signal C4 and the address decode signal C4 is not output.

On the other hand, the MPIJ 4 accesses the Japanese character pattern generator 6 using the address decode signal a (while the clock signal C2 is being output), and when the access is completed, the output of the address decode signal a stops. During this time, one machine cycle (C
1, C3 rises synchronously.

Although falling, one cycle of CI and C3 is called one machine cycle in this embodiment). Therefore, M
The timing at which the Japanese character pattern generator 6 is accessed from the PU 5 is at timing T5 of the next machine cycle.

As shown in Figure 2, the MPU 4 with priority accesses the Japanese character pattern generator 6 in the first machine cycle, and the MPU 5 can access it in the first machine cycle. There is no need to wait for the MPU 5 to access the Japanese character pattern generator 6 during the period from the preparation period for accessing the character pattern generator 6 until the MPU 4 releases access to the Japanese character pattern generator 6. It disappears.

(g) Effects of the invention As described above, multiple MPUs can simultaneously access shared hardware, allocate hardware access time in a time-sharing manner, shorten the time it takes to access hardware, and This has the effect of providing a method for jointly using hardware by a plurality of MPTLs, which can improve the operating efficiency of MPTLs.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a conventional printer device, FIG. 2 is a block diagram of a printer device that is an embodiment of the device according to the present invention, and FIG. 3 is an operational diagram of FIG. 2. In the figure, 1 is a character information buffer section, 2 is a graphic information buffer section, 3 is a printer section, 4 is a character MPU, 5 is a graphic MP0.6 is a Japanese character pattern generator, 7 and 8 are address decodes circuit, 9 and 10 are bus driver circuits,
11 is a frequency oscillation circuit.

Claims (1)

[Claims] In a device comprising a plurality of microprocessors for controlling predetermined means, the plurality of microprocessors are connected to a common path for information transfer and a common path for address transfer via a line drive circuit that sends signals onto the common path. When the plurality of microprocessors simultaneously access the same connected hardware, the plurality of microprocessors access the same hardware in a time-sharing manner. Joint usage method.