JPS6063703A - Data discriminating circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a data discrimination circuit, and in particular to a data discrimination circuit that prevents the phase margin of read data from decreasing even when there is a large instantaneous temporal fluctuation in data input. Regarding discrimination circuits.

[Background of the invention]

Generally, in high-speed magnetic disk drives, etc., a phase synchronization circuit is used to create a timing signal synchronized with read data. It has frequency tracking characteristics for frequency fluctuations in data input, and jitter suppression characteristics for instantaneous timing fluctuations caused by pattern peak shifts, noise, and the like.

FIG. 1 is a block diagram of a well-known phase synchronization circuit, in which a phase comparator 20 detects the phase difference between two signals: data input and CO output. a low-pass filter 30 that smooths the output of the phase comparator 2° to obtain a DC output proportional to the difference between the two signals;
．． A voltage controlled oscillator 40 whose oscillation frequency is controlled by the DC output from the low-pass filter 3°. VC of the oscillator 40
A data discrimination circuit 50 generates a data discrimination window based on the O output signal, discriminates between data (or data and clock) and synchronizes data output according to the input timing of the data input, It consists of a data timing correction circuit 60 that adjusts the timing of data input so that it is centered. FIG. 2 shows an example of a conventional data discrimination circuit 50 in a code recording system in which there is at least one bit "O" between bits "l II and fill+" in the data input.
An explanatory diagram of the operation of FIG. 2 is shown in FIG. The VCO output signal having frequency tracking characteristics for the data input output from the phase synchronized circuit configured as described above is passed through a flip-flop (hereinafter referred to as rFF) in the data discrimination circuit 50.
1 and 1' to generate signals AB, C'D, BC and DA;
and 3, the extended data discrimination window has a width T, +
Generates signals DOW and DIW of ΔTv, respectively F
Fg and 100 input signals. delay circuit cow and 5
The value of the delay time is the set-up time between bit "1" of the data input and the signal AB or CD in FFs 9 and 10, or the switching time ΔT1 of the circuit itself called the hold time, or a value slightly larger than this. is set in advance. Namely, FF9 and.

and 10 input signals, data discrimination window width T, and +ΔTW. If there is no instantaneous timing fluctuation in the data input as described above, only one of the FFs 9 or 10 is set by the data timing correction circuit 60, as shown in FIG. 3(A). That is, either FFQ or 10 is discriminated and set depending on the input timing of data input. When data input "1'" is set to FF9, when signal AB becomes °O", NAND circuit 1-2
．． Through the OR circuit 14, the synchronized data output "1 u" set in the FF15 is obtained by the vCO output signal set and synchronized in the FF15.When the data input "1" is set in the FF10, the signal CD is n O
'', a synchronized de-π output of ``1'' is obtained through the NAND circuit 13, OR circuit 14 and FF 15. Fig. 3 ←) shows the case where there is an instantaneous timing fluctuation in the data input. If there is a small timing fluctuation such as the first and second bits of the data input being "1", an overwhelming data output can be obtained as in the case of &).

However, there is a large timing variation such as the third pit 1", and the signal DOW or DIW from 171 to O'"
If data input is input when switching to FF9
FF9 or 10 may not be set because the set-up time between bit 111 of the data input and the signal DOW or DIW, or the circuit's own switching time called hold time, may not be set. There was a problem that the data was output. That is, for a bit "1" which is an instantaneous fluctuation in timing that is small relative to the data discrimination window width T, +△TW,
Data is discriminated into data (data is divided into four in the MFM recording system), and a data output synchronized with the CO output signal is obtained, but the fluctuation is very large, and the circuit elements of the data discrimination circuit are If the data input bit "1" is input within the switching time of the circuit itself, which is determined by the performance, the above-mentioned problem occurs, which causes the problem that the phase margin of the read data decreases. .

Figure 4 shows MFM (Modified Freq
FIG. 3 is an explanatory diagram of a recording method (uency Mod, qlation).

This method, like the NRZI method, uses bits
'The magnetization is reversed, and the magnetization is not reversed when the pin is "O".

The MFM method is FM (Frequenoy Mod
u4ation-) method and PM (Phase M
odu! tion) method: Since the frequency of boride inversion is about half, high density is possible, but the reproducing circuit becomes complicated. Also, as the self-clocking method excels, when the bits "O" and "0"' occur consecutively, the magnetization is reversed in the middle of the bits.

@4 As shown in Figure 4, the output voltage when a medium recorded with the MFM recording method as "101100'" is read by the reading head becomes the data input of the discrimination circuit. In other words, data input provides reading information "°l" with a pulse width of T/2 or more at the rise and fall of the magnetization state on the medium, and at other positions, information "0" is given at a period of 'r/2. "give.

Also in the MFM recording method, the data discrimination window width.

For T1+△T, data input pitch h ” 1
If the fluctuation in the FF is extremely large and a data input of 1) is input within the switching time of the data discrimination circuit, the FF
If 9 or 10 is not set, it will give incorrect data output.

(Objective of the Invention) The object of the present invention is to solve such conventional problems and to provide a system in which the phase margin of the read data does not deteriorate even when there is a large instantaneous fluctuation force1 in the data input. The object of the present invention is to provide a data discriminator circuit with the following features.

[Summary of the invention]

In order to achieve the above objects 1i-i, the data valve St+ of the present invention
The circuit generates a data discrimination window based on the output of the phase-locked circuit, and uses the data discrimination window in a data discrimination circuit that discriminates data or clock and synchronizes data output according to the input timing of data input. The present invention is characterized in that it has means for setting the data discriminated by , and means for further setting the data set in the data setting means from the output C of the phase locked circuit.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be explained with reference to the drawings. Fig. 5 is a block diagram of a data discrimination circuit showing an example of the implementation of the present invention, and Fig. 6 shows the operation time of Fig. 5.・It is a chart. The circuit of this embodiment is characterized by the provision of data set circuits 17 and 18 consisting of a NAND circuit and a NOR circuit. That is, in FIG. 5, the VCO output, which is output from the phase synchronized circuit and has frequency tracking characteristics with respect to data input, is frequency-divided by FF1], signals AB and CD.
occurs. These signals pass through discrimination window expansion circuits 2 and 3 consisting of delay circuits 4 and 5 and OR circuits 6 and 7 to generate signals DOW and D I W with an expanded data discrimination window width Tw+ΔT, respectively. It becomes an input signal for data set circuits 17 and 18. On the other hand, data input generates a signal DATA through the FF 16, which becomes an input signal to the data set circuits 17 and 18 like the signals DOW and DIW mentioned above.

If there is no temporary timing fluctuation in the data input as shown in FIG. 6(a), the timing correction circuit 60 sets the data input in advance to be at the center of the pulse widths of the signals DOW and DIW. The signal DATA matches the input conditions of the NAND Y° circuit 710 when the DOW car is "O", and becomes an input signal to the NAND circuit 19 through the NOR circuit 76. Further, since the data output signal has not yet been generated and is 0'', the data set circuit 17 for matching the input condition of the cant circuit 190 is set and generates the signal DOI.

Next, the input signal AB1 of the NAND circuit 74! When the conditions of +Z"O" and BC are 0" are met, the FF9 power is set and the signal DO is generated, which is the input signal of the pear 1 circuit 120.

becomes. When the signal CD becomes "0", the signal DOD is issued through the circuit 12, becomes the input signal of the FF 15 through the OR circuit 14, and the CO output signal:
Set to FF15 to obtain data output. On the other hand, when the signal D1wit becomes ``o'', the data set circuit 1
8 is also set and generates signal DLL. However, since the data output number has already been generated by the signal DQD and the CO output signal, FFl0 is in the reset state and the FFQ
It is discriminated as either the side or the FF10 side. When the signal DIW is "O", if the aforementioned data input comes, the NAND circuit 73.
Data set circuit 1 consisting of 72 and NOR circuit 77
6 is set, and when the signals CD and DA become 'O'', FFl0 is set, and the NAND circuit 13.OR circuit 1
4 and FF15 to obtain data output. Figure 6←
) indicates a case where there is an instantaneous timing fluctuation in data input. If the fluctuation is a small fluctuation such as the 1st and 2nd Bi-Rad 1” of data input, please refer to Figure 6 (Pi).
As shown in , it is correctly discriminated as FF9 or FF10. Furthermore, the third bit of the data input, 1", indicates the case where the fluctuation is very large, and there is input data when the signal DOW is switched, but the data set circuit 18 is through, FFl0 is set,
When the signal AB becomes '0''', it is input to the FF through the NAND circuit 13 and the OR circuit 14, and normal data is output by the CO output signal. [Effects of the Invention] As explained above, according to the present invention, By providing two data set circuits, one for setting the data discriminated by the window and the other for further setting the data set in the data set circuit by the output of the phase synchronization circuit, data input is possible. This provides a remarkable effect in that it is possible to realize a data discrimination circuit that prevents the phase margin of read data from deteriorating even when there is a large temporal fluctuation.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a phase synchronization circuit, Fig. 2 is a diagram showing a conventional data discrimination circuit, Fig. 5 is an operation time chart of Fig. 2, and Fig. 4 is an operation time chart of MFM recording method. The figure is a block diagram of a data discrimination circuit showing one embodiment of the present invention, and FIG. 6 is an operation time chart of FIG. 5. 1.9.10,15,16: Flip Flop 2p, 2,
3: Data discrimination chamber expansion circuit, 4, 5: Delay circuit, 11+
Data output discrimination circuit, 2Q+Ikawa 1 comparator, 40: Voltage controlled oscillator, 17, 18: Data set circuit.

Claims (1)

[Claims] (1) In a data discrimination circuit that generates a data discrimination window based on the output of a phase-locked circuit and performs de-transfer or clock discrimination and synchronization of data output depending on the input timing of data input, discrimination is performed using the data discrimination window. 1. A data discrimination circuit comprising: means for setting the data set in the data setting means; and means for further setting the data set in the data setting means using an output of a phase synchronization circuit.