JPS6064529A - Circuit for decoding bch single error correction and double error detection code - Google Patents

Abstract

PURPOSE:To attain a BCH decoding circuit without any erroneous correction by discriminating a 1-bit error and >=3 of odd number bit errors, applying correction to 1-bit error and applying correction command to an error of >=2-bit. CONSTITUTION:A decoding circuit of a BCH single error correction/double error detection code decoding circuit consists of calculation circuits 1, 2, a delay circuit 4, a detection circuit 3, exclusive OR circuits 8, 9, a latch circuit 7A, and an AND gate 10. Calculation circuits 1, 11 calculate a syndrome F(1) and calculation circuits 2, 12 calculate F(alpha). An output of the F(1) and F(alpha) identifies whether the error is 1-bit error or >=3 of odd number bit error, the 1-bit error is applied with the correction and the error of >=2 bits is applied with correction command operation.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention BCH (Bose-Chaudhuri-
Hocquenghem) Regarding the BCH single-error re-correction/double error-detection code decoding circuit that decodes the single-error re-correction/double error-detection code, I would like to further comment on the television satellite broadcasting S-■ receiver, etc. The present invention relates to a BCH single-error recorrection/double error detection code decoding circuit used for.

(Prior Art) In television satellite broadcasting, audio data and independent data are encoded using BCH (63, 56) single error correction (SEC)/double error detection.

BCH (63, 56) SEC-DED code generator polynomial〇 (x) is G(x)=X7+X6+X2+1-
It is given by (X+I XX6+X+1).

A BCH8EC-DED code decoding circuit for decoding such a coded signal was constructed as shown in FIG.

The above encoded reception signal F (reception polynomial F(X)) is supplied to the input terminal IN. l is the receiving polynomial FC)
Calculate syndrome F(1) by dividing by t(x+1),
It is a calculation circuit that generates a binary output corresponding to the syndrome F(1), and 2 is a calculation circuit that generates a binary output corresponding to the syndrome F(1).
X6+X+1) and divide by syndrome F←) [α is (
3 is a calculation circuit that calculates the root of
This is a detection circuit that generates an error correction output corresponding to 4 is a delay circuit that delays the received signal for a period of 63 bits.

The output of the calculation circuit 1 is supplied to an inverter 5 and inverted, and the output of the inverter 5 and the detection output from the detection circuit 3 are supplied to an AND gate circuit 6 to detect a double error, and the output of the AND gate circuit 6 is is supplied to the latch circuit 7 as a correction instruction signal EP, and the correction instruction signal EP is supplied to a correction circuit (not shown) to perform correction operations such as pre-hold correction or average value interpolation correction.

On the other hand, the received signal F delayed by the delay circuit 4 and the detection circuit 3
The corrected output output from is supplied to an exclusive OR circuit 8 as a correction means, and the received signal F is inverted by 1 to obtain a corrected received signal CF. Therefore, when using a decoding circuit configured as described above, (f) F(
1) = 0, F) = 0, it is determined that there is no error, ←) F(1) = 1, F), when NO, it is determined that there is no error.
It is determined that it is an error and correction is performed, and (c) F(1)=0. F
) When the value is 40, it is determined that the chain is double stranded and correction is performed.

Therefore, (4) 0) No false bits, ←) Even bits l)
When the syndrome F(b) = 0, (B) an odd number bit is wrong and the syndrome F(b) = 0, no correction is performed, (C) an even number bit is wrong and the syndrome F) = When it is 1, correction and correction operations are performed, and (b) when syndrome F(b)=1 in an odd bit error, a correction operation is performed.

However, a block of the BCH (63, 56) 8EC-DED encoded received signal F includes, in addition to audio data, range bits that are audio signal compression information and independent data.

However, when using the above-mentioned conventional decoding circuit, 63
In the case of error of only 1 bit in pit block, it is correctly corrected and decoded. As a result of the simulation, correct decoding operation cannot be expected when there is an odd number of errors of 3 or more bits. This method has the disadvantage that there is a high probability of erroneous corrections being made.

Therefore, the range bit in the 63-bit block,
This miscorrection is a problem for independent data.

(Object of the invention) The present invention has been made in view of the above,
By identifying 3 or more odd bit errors, performing a correction operation for a 1 bit error, and instructing a correction operation for 2 or more bit errors,
It is an object of the present invention to provide a BCH8EC-DID ID code assimilation circuit that eliminates the above-mentioned drawbacks.

In the present invention, once decoded data is supplied to the calculation circuit again to perform syndrome calculation, and the syndrome p*(+
) and F, (b) are zero, the first decoded data is the decoded output, and the syndrome F! (1) and F
, @ are not zero, a correction command signal for performing correction is output.

The present invention will be explained below with reference to Examples.

(Configuration of the Invention) FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention.

The received signal supplied to the input terminal IN is supplied to a calculation circuit 11, a calculation circuit 2, and a delay circuit 4 for a 63-bit period. The output of the calculation circuit 2 is supplied to the detection circuit 3, the detection output of the detection circuit 3 and the output of the calculation circuit 1 are supplied to the exclusive OR circuit 9, and the output of the exclusive OR circuit 9 is supplied to the latch circuit 7A and latched. It is configured to do so. Latch circuit 7A
The inverted latch output n and the correction output of the detection circuit 3 are supplied to an AND gate circuit 10, and the output of the AND gate circuit 10 and the received signal F delayed by the delay circuit 4 are supplied to an exclusive OR circuit 8 as a correction means. It is.

The decoding circuit is configured as described above.

The output of the exclusive OR circuit 8 is sent to the calculation circuit 11 and calculation circuit 1.
2 and the delay circuit 14.

The calculation circuit 11 calculates the output k (x+1
) to calculate the syndrome F(1) and generate a binary output corresponding to the syndrome F(1), and is configured similarly to the calculation circuit 1. Calculation circuit 12
is the output of the exclusive OR circuit 8 as a primitive polynomial (X'+X+1
) and calculates the syndrome F@, and is configured similarly to calculation circuit 2. The delay circuit 14 is a delay circuit that delays the output of the exclusive OR circuit 8 for a period of 63 bits.

The output of the delay circuit 4 is supplied to a delay circuit 13 which delays the input by a period of 63 bits, and the output of the delay circuit 13 and the output of the delay circuit 14 are supplied to a selector 15. On the other hand, the latch output EP of the latch circuit 7A has an input of 1
The signal is supplied to a delay circuit 16 which delays the block period (=the period of the 63 bits).

The F calculated by the calculation circuit 12, that is, the output of the calculation circuit 12, is supplied to the detection circuit 17 which generates a detection output to determine whether F is 0'' or not. The output of the calculation circuit 11 is supplied to the or-dirt circuit 18, and the output of the or-dirt circuit 18 is supplied to the selector 15 as a selection signal.

The selector 15 is configured to select and output all outputs of the delay circuit 13 when the output of the OR gate circuit 18 is at a high potential, and to select and output the output of the delay circuit 14 when the output of the OR gate circuit 18 is at a low potential. It is.

The output of the OR gate circuit 18 and the latch output EP delayed by the delay circuit 16 are supplied to the OR gate circuit 19, the output of the OR gate circuit 19 is supplied as a correction instruction signal to a correction circuit (not shown), and the output of the OR gate circuit 19 is The configuration is such that the correction operation is performed by.

Note that the delay circuits 4, 13, 14, and 16 are provided to synchronize the timing, and may delay by a period of 64 bits.

(Function of the Invention) In the embodiment of the present invention configured as described above, the calculation circuits 1 and 2, the detection circuit 3, the delay circuit 4, and the exclusive OR circuit 80 operate as in the conventional example shown in FIG. However, the outputs of the calculation circuit 1 and the detection circuit 3 will be explained.

Calculation circuit 1 calculates syndrome F(i) by dividing by reception polynomial F(x)'fc(X+1), and calculates syndrome F(i).
(1) Low potential output when 20, syndrome F (1)
+.

Generates a high potential output when . The calculation circuit 2 divides the received polynomial F(X) by (X'+X+1) to calculate the syndrome F(b). The detection circuit 3 receives the syndrome F@ calculated by the calculation circuit 2, and generates a low potential output when F(b)=0 and a high potential output when F(b)Mo, and F(< +o, a high potential output is generated as a correction output in response to an erroneous bit.

Similarly, the calculation circuit 11 divides by the polynomial t(x+1) formed by the output of the exclusive OR circuit 8, and calculates the syndrome F(1
), and when the syndrome F(1)=0, a low potential output is generated, and when the syndrome F(1))O, a high potential output is generated. Calculation circuit 12 receives the same signal as calculation circuit 11 and divides it by (X6+X+1) to calculate syndrome F(b). The detection circuit 17 receives the syndrome F(b) calculated by the calculation circuit 12 and generates a low potential output when F(b)-0, and a high potential output when F(<+o) as a detection output.

Therefore, the syndrome F(1) calculated by the calculation circuit 1 for the received signal F and the syndrome F(1) calculated by the calculation circuit 2 according to the value of d- are shown in Table 1. It becomes like this.

Table 1 Therefore, in one embodiment of the present invention, the generation of the correction instruction signal and the correction operation for the 74 erroneous turns shown in Table 1 are as follows.

First, in case A, the output of the exclusive OR circuit 9 is at a low potential and no correction instruction is given, and the latch circuit 7
Although the inverted output 11- of A is at a high potential, since F(b)=0, no correction output is generated from the detection circuit 3, and therefore no correction operation is performed. That is, in case A, it is determined that there is no error, and no correction operation is performed and no correction instruction is issued.

Next, in case B, the output of the exclusive OR circuit 9 is a high potential output, and the latch output EP of the latch circuit 7A is a high potential! It is outputted as output EF via extension circuit 16 and OR gate 19, and a correction instruction is issued. Furthermore, the inverted output node of the latch circuit 7A becomes a low potential, and the AND gate circuit 10 is controlled to have its dart closed.

Further, the detection circuit 3 does not generate a correction output. Therefore, no corrective action is taken. Therefore, in case B, although it is a single error, a correction operation is performed.

In case B, the audio data was previously unprocessed and overlooked, but now the audio data can be corrected.

Next, in case C, the output of the exclusive OR circuit 9 is at a high potential, and the latch output EP is at a high potential.
Correction instructions are given in the same way as in the case of . The dart of the AND gate circuit 10 is controlled to be closed by the inverted output of the latch circuit 7A, and although a correction output is output from the detection circuit 3, no correction operation is performed. That is, case C
In this case, it is determined that there is a double error and only the correction operation is executed.
No corrective action is taken. Therefore, when a correction algorithm is used, if correction is also performed at the same time, there is a high probability that the range bits and independent data will be incorrectly corrected as a result of simulation, but as described above, only the correction operation is performed and no correction operation is performed. The final range bits and independent data are not incorrectly corrected, and the risk of errors in the range bits and independent data can be avoided. Furthermore, since correction means such as previous value retention and average value interpolation are available for audio data, there is no operational problem with the correction.

Next, in case D, the output of the exclusive OR circuit 9 is at a low potential, the latch output EP is at a low potential, and no correction instruction is given. Further, the inverted output EP of the latch circuit 7A becomes a high potential, and the dart of the AND dart circuit 10 is controlled to be open, and the correction output output from the detection circuit 3 is sent to the exclusive OR circuit 8 via the AND gate circuit 10. supplied,
The erroneous bits of the received signal F delayed and outputted by the delay circuit 4 are inverted by the correction output, and a correction operation is performed. That is, in case D, it can be determined that an odd number of bits are erroneous, and only a correction operation is performed.

Next, the output of the exclusive OR circuit 8 is calculated by the calculation circuits 11 and 1.
2, the output px of the exclusive OR circuit 8
The syndrome F(1), F) is calculated for (x). If we use the expression F2(1), F, CCt) for the result of this second syndrome calculation, we can obtain case n0(F2(1)-01F2) depending on the state of Fg(1), Fg(''). @)=0), Case DI U”* (1) Jealousy 0, p2(a)−〇)
.

Case n, (F2(1)=O, Fz@'=0)
, case D3 (Fg(1)'= O, p, (b)'=
O) is possible.

In case D0, the output of the calculation circuit 11 and the detection output of the detection circuit 17 are both at a low potential, the output of the OR-DART circuit 18 is at a low potential, and the selector 15 outputs the output of the delay circuit 14, that is, the exclusive OR. The delayed output of the circuit 8 is selected and output from the selector 15 as a decoded output.

In case D1, the output of the calculation circuit 11 is at a high potential, and the detection output of the detection circuit 17 is at a low potential. In case D, the output of the calculation circuit 11 is at a low potential, and the detection output of the detection circuit 17 is at a high potential. In case D, the output of the calculation circuit 11 and the detection output of the detection circuit 17 are at high potential. Therefore, in the case D1 y D2 r DB, the output of the OR gate circuit 18 is at a high potential, and the selector 15 selects the received signal Fi delayed from the output of the delay circuit 13, that is, the output of the delay circuit 4, and outputs it to the selector 15 as the decoded output. is output from. On the other hand, the output of the OR/DART circuit 18 is output as a correction instruction signal via the OR gate circuit 19, and is corrected by a correction means (not shown).

However, in cases A, B, and C, the it reception signal F is sent out from the exclusive OR circuit 8 without being corrected as described above. Therefore, case A becomes case D0, case B becomes case D, and case C becomes case D. Therefore, in case A, the selector 15 outputs the output of the exclusive OR circuit 8 delayed by the delay circuit 14 as the decoded output, but there is no problem since it is not corrected. Of course, no correction is made.

Next, in cases B and C, the selector 15 outputs the received signal F delayed by the delay circuits 4 and 13. However, in cases B and C, since the correction is made, in this case, the output of the exclusive OR circuit 8 and the received signal F delayed by the delay circuit 4 are the same, and the selector 15 output, delay circuit 14
The decoding output is the same even if the output slope is selected. In this case, a correction instruction is also given.

In case D, the received signal F delayed by the delay circuit 4 is corrected by the exclusive OR circuit 8, and the corrected received signal F is supplied to the calculation circuits 11 and 12 to generate the syndrome Fffi(1). , pi @ 7% total N,
When F, (1) = O and F, (b) = 0, that is, case D0, it was determined that there was an odd number of bit errors in case D in the previous process, but it was actually a one bit error. It is determined that it was Therefore F, (1)=
0 and F! )=0, it is possible to distinguish between an odd number of bit errors of 93 or more and a 1-bit error.

This is because a 1-bit error is correctly corrected in the decoding circuit. In case D0, as in case A, the receive signal F corrected by exclusive OR circuit 8 in selector 15 is output as a decoded output. In this case, no correction is made.

Also, in case D, F, (1) = 0 and F! @＝
.

If not, case Di r D2 occurs. Case D will also occur with a low probability. In the case of case D, when case D1 + D, l D3 is obtained, correction has been made in case D in the previous process, but since the selector 15 selects the output of the delay circuit 13, the output from the delay circuit is used as the decoded output. 4 and 13 are output, a correction instruction signal is output from the or-dart 19, and a correction operation is performed.

In this case, the correction instruction is not carried out in case D of the previous step, but as described above, the correction instruction signal is outputted so that the uncorrected received signal is output as the decoded output, and the correction operation is performed. Alternatively, the delay circuit 16 and the OR gate 19 may be omitted, and only the output of the OR gate 18 may be used as the correction instruction signal.

(Effect of the invention) According to the present invention, F(
1) Only correction is performed when = 0 and F) lol 0 or when F (1) lol 0 and F) - 0, so processing that was previously overlooked is now performed in the form of correction. I will do my best to help you. Also, in the second syndrome calculation, F, (1
) = 0 and F, the output from the correction means is the decoded output only when ) = 00, and when F, (1) = O and F, (b) = 0, the supplied original signal is the decoded output. In addition, since the correction instruction signal is output to cause the correction to be performed, the corrected signal is output only when the supplied signal has a 1-bit error. A corrected decoded output is obtained. Furthermore, except when F, (1) = O and F, (b) = 0, the supplied original signal is output as the decoded output, and the correction instruction signal is output to perform the correction.
Erroneous corrections will no longer be made and output. Therefore, when multiple bit errors occur, corrections are made without being incorrectly corrected. However, it is possible to correct audio data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional BCH8EC-DED code decoding circuit. FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention. 1.2, 11 and 12... calculation circuit, 3 and 17
...Detection circuit, 4, 13.14 and 16...Delay circuit, 7A...Latch circuit, 8 and 9...Exclusive OR circuit, 10...And dart circuit, 15...Selector . Patent applicant: Nobuo Sunako, patent attorney representing Trio Co., Ltd.

Claims (1)

[Claims] a second calculation circuit that calculates the root of the BCH single error correction/double error detection coded polynomial; and a detection output that determines whether or not the output of the second calculation circuit is zero. a first detection circuit that generates an error correction output corresponding to F); and a first detection circuit that generates an error correction output corresponding to F;
← When UF(1)'=0 and F) is NO, and when UF(1)'=O and F) is 0, the correction instruction means generates a correction instruction output, and the correction output of the first detection circuit is used. a correction means for correcting a predetermined bit of the signal; a dirt means for cutting off the correction output of the first detection circuit according to the inverted output of the correction instruction means;
! (t) *A third calculation circuit that calculates, a fourth calculation circuit that calculates syndrome F momo, and a second detection circuit that detects whether F and @ are zero from the output of the fourth calculation circuit; According to the output of the third calculation circuit and the output of the second detection circuit, when Ft pg(t)=o and F, (b)=0, the output of the correction circuit is taken as the decoded output, and F*(1)=o and F, (b): a BCH single-error re-correction/double-error detection code, comprising: selection means for making the signal a decoded output and generating a correction instruction output when the signal is other than 0; decoding circuit.