JPH03250817A - Error correction circuit - Google Patents

Abstract

PURPOSE:To improve the correction capability by using a final threshold level only more frequently for decoding processing than other threshold levels in a majority decision logic element used for the teletext broadcast or the like and applying decoding under the variable threshold level. CONSTITUTION:The circuit is provided with a syndrome register 1, a majority decision circuit 2, a timing generating circuit 3, a data register 4 and an error check circuit 5. After the timing generating circuit 3 detects a final threshold level and the correction at the final threshold level is finished and an error check flag of the error check circuit 5 is set, that is, an error still exists anywhere, the error correction is circulated again with the same final threshold level. Thus, when the error is an error of 8 bits or below just before the final correction, the error is corrected. Then the substantial error correction capability is improved.

Description

[Detailed Description of the Invention] [Industrial Field of Application 1] The present invention relates to an error correction circuit, particularly a decoding circuit for error correction codes used in teletext broadcasting, etc., which conventionally improves correction ability by using a variable threshold. The performance was improved by further devising the circuit.

[Summary of the Invention 1 The present invention provides a code that can be decoded by a majority logic element that decodes with a variable threshold used in teletext broadcasting, etc., by decoding only the final threshold more times than the other thresholds. This decoding circuit has improved correction capability compared to the previous decoding circuit.

Although the present invention can be applied to a decoding circuit for codes that can be decoded by most majority logic elements, for convenience of explanation, we will specifically explain the code using (272.190) codes used in teletext broadcasting. It is explained below in an easy-to-understand manner.

[Prior art] Figure 3 shows a conventional error correction circuit (Japanese Patent Application Laid-Open No. 59-18184
1) shows the flow of the algorithm after data loading.

Since the (272,190) code is one bit shortened from the original (273,191) code, one correction period is 273 bits. The first bit is assumed to have been sent as O and is not corrected. In these conventional decryption methods,
Even when the correction is completed at the final threshold of 8 or 9, there may still be errors of 8 bits or less that can be corrected with this code. In particular, the number of error bits is 15 to 1 out of 272 bits.
It seems that in many cases it is 6 bits or less.

In Figure 3, after loading 272 bits of data into the data register and syndrome register, the original threshold is set to 9 (or 8) or higher (Sll
) After completing the first correction for all bits (S12, 513), it is checked whether all syndrome registers are set to O (S14). If all the syndrome registers are O, the correction operation is stopped, and it is assumed that the correction has been made, and packet processing begins (S15). Note that, of course, the contents of the syndrome register are checked before starting this error correction operation, so FIG. 3 should be interpreted as a case where the contents of the syndrome register are not 0 at the beginning.

In S14, the syndrome register becomes 0 with one correction.
If not, it is checked whether L is the final threshold of 9 (or 8) (316). If the final threshold has not been reached in S16, L=L-1 in S17.
Then, the process returns to S12 and the same error correction is performed again. S1
If the final threshold value has been reached in step 6, it is interpreted that an error still remains, and error detection processing is performed in step S18.

In this way, in conventional circuits, the threshold value is set to a high value to perform rough error correction, the threshold value is gradually lowered, and the original correction is performed at the final threshold value, thereby improving the correction ability. It is.

[Problem to be Solved by the Invention 1] However, in the above-mentioned conventional circuit, even at the end of correction at the final threshold, errors of 8 bits or less, which is the original correction capability of this code, may remain.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an error correction circuit that performs correction using the final threshold value again in order to correct such errors, thereby substantially improving the error correction ability.

[Means for Solving the Problems 1] In order to achieve the above object, the present invention includes a detection circuit for detecting a final threshold value in a variable threshold decoding circuit, and multiple decoding methods for decoding data at the final threshold value based on the detection result of the detection circuit. It is characterized by comprising a means for processing.

[Function 1] According to the present invention, with the above configuration, multiple decoding processes are performed using the final threshold value, and the error correction ability is improved.

[Example 1] Hereinafter, the present invention will be described in detail based on an example shown in the drawings.

FIG. 1 is a block diagram of an error correction circuit according to the present invention, in which 1 is an 82-bit syndrome register, 2 is a majority decision circuit, 3 is a timing generation circuit, 4 is a 272-bit data register, and 5 is a block diagram in which register 1 is all O's. An error detection circuit that detects whether or not the error occurs.

The timing generation circuit 3 includes a CPU, a ROM storing a control program for the CPU, and a storage area L described later.
Data temporary storage area and data register 4 with L=9
The inputs to this timing generation circuit 3 are a clock signal, a load signal indicating the beginning of data or a data period, and an error detection circuit 5. A signal from the source is sufficient. A clock signal, a load signal and a signal from the error detection circuit 5 generate all the signals necessary for this error correction circuit in the timing generation circuit 3. However, in FIG. 1, only the threshold value control of the majority circuit 2 is shown as the output signal of the timing generation circuit 3, and other output signals are omitted.

Next, the second section will discuss the operation of the error correction circuit configured as described above.
This will be explained with reference to the figures.

First, after loading the uncorrected data into syndrome register 1 and data register 4, timing generation circuit 3
sets the threshold of majority circuit 2 to 9 or more (Sl)
. Next, only syndrome register 1 is shifted by 1 bit (S2), and errors are corrected for all 272-bit data in data register 4 (S3). This error correction is performed as follows.

That is, the signal from the syndrome register 1 is compared with the threshold value in the majority circuit 2 determined by the signal from the timing generation circuit 3, and the circuit 2 outputs an error correction signal. This error correction signal is added to the output of the data register 4 and circulated within the data register 4, thereby performing error correction for all 272 bits. Note that the error correction signal can also be returned to the syndrome register 1.

Next, the timing generation circuit 3 detects whether all of the syndrome registers 1 are "0" based on the signal obtained through the error detection circuit 5 (S4), and if it is "O", the corrected data is taken out from the data register 4. Proceed to packet processing (S5), and if it is not "0"', the timing generation circuit 3 determines whether L=9 in S6, and if L=9 is not, proceed to S7
Then, the value of L is decreased by one and the process returns to S2, and when L=9, the process proceeds to S8. Note that the timing generation circuit 3 initially
=9, the flag is set to "1".

At S8, refer to the flag of the timing generation circuit 3 and set L=
Check whether the correction has been made twice in step 9, and if not, press S.
Return to step 2 and repeat the correction operation, and if it has been done twice, S9
Performs error detection processing.

Note that although the final threshold value is set to 9, it is natural that the same effect can be obtained even if the final threshold value is 8. Further, although the threshold value is lowered by 1, it is natural that the same correction effect can be obtained by lowering the threshold by 2 or 3. Further, although the final threshold value is corrected twice, it is natural that the same effect can be obtained by performing the correction three or four times, although it takes more time. It goes without saying that the same effect can be obtained even if correction is performed multiple times for each threshold value.

As described above, after the timing generation circuit 3 detects the final threshold value and completes the correction operation using the final threshold value, if the error detection flag of the error detection circuit 5 is set, that is, there is still an error somewhere. In some cases, error correction is performed once again using the same final threshold value. This makes it possible to correct any errors of 8 bits or less immediately before the last correction operation.

[Effects of the Invention] As explained above, according to the present invention, in the conventional decoding method, correctable errors may remain at the end of the decoding process, but multiple errors may remain at the final threshold. By performing the correction, it was possible to correct all of those errors, thereby improving the substantial error correction ability. The circuit scale can be realized with almost no change compared to conventional circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an error correction circuit according to the present invention, FIG. 2 is a flowchart showing the operation of the error correction circuit, and FIG. 3 is a flowchart showing the operation of a conventional error correction circuit. 1...Syndrome register, 2...Majority circuit, 3...Timing generation circuit, 4...Data register, 5...Error detection circuit.

Claims (1)

[Claims] 1) An error correction circuit characterized in that the variable threshold decoding circuit includes a detection circuit for detecting a final threshold, and means for performing multiple decoding processes on data using the final threshold based on the detection result of the detection circuit.