JPS6064573A - Picture signal reducing system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an image signal reduction method used, for example, when reducing an image signal obtained by a photoelectric conversion unit of a facsimile machine or the like.

[Technical background of the invention]

In the conventional image signal reduction method, a memory is prepared in advance in which B-bit reduction data is stored in accordance with the A-bit address, a binary image signal is input to the memory as an address, and the data is stored in this memory. The B-bit data outputted from the B-bit data was used as a reduced image signal.

For example, when reducing both 3-bit signals to 2-bit signals, as shown in Table 1, the 3-bit input and 2-bit output are Use memory.

Table 1 In Table 1, R@@ stores the data shown in the R column of the same table instead of the data in the data box for the addresses in rows 0 and f. This shows that it is also possible to use memory with

Here, when the 9-bit image signal shown in rows i to 1 of P in Table 2 is reduced using a memory in which addresses and data are associated as shown in Table 1, the corresponding The 9-bit image signal 11F2 is reduced to both 6-bit signals shown in rows i to 1 of table Q.

[Problems with background technology]

The 9-bit image signals shown in PsO rows 1 and j of Table 2 are from white (0) bit to black (1) bit, respectively.

The change from the black (1) bit to the white (0) bit remains even if the image signal is reduced to the 6-bit image signal shown in the i and j rows of the Q column.

However, when both the 9-bit signals shown in row 1 and row 1 of Ps are reduced to the 6-bit image signals shown in row 1 and row 1 of column Q, the signals shown in row 2 and row 4 of P The 4th white (0) bit from the first bit (the leftmost bit in Table 2) of the 9-bit image signal shown is divided by 1, and the black (1) bit is divided by the white (0) bit, and then the black (1) bit is divided by 1. There was a drawback that changes in the image signal that changed to bits were not retained.

[Purpose of the invention]

The present invention was made in view of the drawbacks of the conventional image signal reduction method as described above, and its purpose is to
1) Change from bit to white (0) bit or white (
An object of the present invention is to provide an image signal reduction method capable of preserving the change from 0) bit to 1) bit as much as possible.

[Summary of the invention]

Therefore, in the present invention, a serial-to-parallel converter converts the serially input binary image signal into parallel and outputs the A-bit portion, and the A-bit image signal output from the serial-to-parallel converter is input as an address. A memory that outputs B pit data stored in advance corresponding to this address, a parallel-to-serial converter that inputs the data output from this memory, converts it into serial data, and outputs it, and The timing of loading data into the parallel-to-serial conversion section, the timing of outputting the data loaded into this parallel-to-serial conversion section from this parallel-to-serial conversion section, and the reading out of the data output from this parallel-to-serial conversion section as an image signal. and a timing control section that controls the timing, and each time an image signal of A-1 bits or less is sequentially input to the serial/parallel conversion section,
By applying a load signal instructing the load timing to the parallel-to-serial converter, both signals below the A-1 bit are reduced to B bits by referring to at least one bit before and after the A-1 bit. and achieved the above objectives.

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an image signal reduction device employing the method of the present invention. In the figure, 1 is a shift register which is a serial-to-parallel converter. This shift register 1 is an 8-stage shift register, in which an original image signal is serially input from the SI terminal, and a read lock E is applied to the CK terminal.
The image signal is shifted one bit at a time in synchronization with the rising edge of the pulse.

The outputs of each stage of the shift register 1 are applied to address terminals M to A7 of the ROM 2. This ROM 2 stores 5 bits of data in accordance with the given 8 bit address, and outputs 5 bits of data in accordance with the given 8 bit address. In Table 3,
The correspondence between addresses and data in ROM2 is shown.

Margin below: The ROM 2 in which addresses and data are associated as shown in Table 3 is designed with the following points in mind.

■ Address terminal Av = 6 bits in the center of At, leaving the pattern of the 6-bit image signal 1 to AsK applied to the address terminal of The image signal is deleted to create 5-bit data.

■ 1-bit image signals stored in 1-bit address terminals A, , A, at each end of address terminal Ao''Ay - that is, 1-bit image signals before and after the image signal to be reduced (this specification refers to If we say that the first 1-bit image signal of the image signal is to be reduced from the nth visit to the n-1-mth bit in the middle box of a series of image signals, then
The previous 1-bit image signal refers to both of the n-1-th bit signals, and the subsequent 1-bit image signal refers to the n-4-m+1-th bit image signal. ) -, try to preserve as much as possible the change from white (0) bit to black (1) bit in the original signal, the transition from black (1) bit to white (0) bit, and the change from black (1) bit to white (0) bit. . For example, the third
As shown in the table, both signals applied to address terminals Ao to A7 are (000oo16o) and (00000101
). The central 6 bits of these two signals (the image signals to be reduced) are both (000010), so if we only take into account the above caution, we can convert the image signals of the above two examples into the same image signal ( ooool ). However, if we also take into account the precautions in (■) above, we can reduce the image signal (00000100) to the image signal (00001) and convert the image signal (oooootol) to the image signal (00010).
should be reduced to In this way, the ROM 2 is created by storing 6-bit data corresponding to each address.

Note that, for example, a 6-bit image signal to be reduced by n is (01
0101), it may be impossible to reduce the size in consideration of the above precautions (2).

That is, the image signal (101010
10) is given. In this case, the data to be stored at the corresponding address is determined by taking into account the caution in (2).

The data output from the output terminal Qo=Q4 of the ROM 2 in which data has been stored in this manner is loaded into the shift register 3, which is a parallel-to-serial converter. The timing of loading the data output from the upper FROM 2 into this shift register 3 and the timing of shifting the data loaded into this shift register 3 are determined by the timing control unit 7.
Consider shift register 3. That is, the timing control section 7
When the load signal G output from the ROM 2 is activated (low level) and reaches the load terminal LOAD of the shift register 3, the data output from the ROM 2 is loaded. Further, the shift clock C output from the timing control section 7 is applied to the CK terminal of the shift register 317', and data in the shift register 3 is shifted in synchronization with the rising edge of the pulse of the shift clock C.

The timing control section 7 includes a hexadecimal counter 4, a Nantes gate 5 which is a first logic gate, and an OR gate 6 which is a second logic gate. The read lock E is applied to the CK terminal of the counter 4, and the counter 4 counts up in synchronization with the rising edge of the read lock E pulse.

The counter 4 outputs the carry F from the C'RY R terminal as a high level every time six pulses of the read lock E arrive. In addition, the Nantes gate 5 has a counter 4.
The carry F output from the kidney clock E and the kidney clock E are input. The output of the Nant gate 5 is applied as a load signal G to the low terminal LOAD of the shift register 3. Furthermore, the carry F output from the counter 4 and the read lock E are input to the OR gate 6. The output of the OR gate 6 is applied as a shift clock C to the CK terminal of the shift register 3. Furthermore, the data output from the SO terminal of the shift register 3 is applied as a reduced image signal D' to the readout circuit 10. The circuit 10 reads out the data output from the SO terminal of the shift register 3 as a reduced signal D' at the falling timing of the shift clock C.

The operation of the image signal control device configured as described above is as follows.
The explanation will be made with reference to FIGS. 1 and 2.

First, in the first state, 1rl in shift register 1
:, all zeros, and the same 1 at the rising edge of the pulse aQ of the *fJ7j7 clock E of the second river (see, the first two signals (0) are input to the shift register 1, I-4-
Ru. Next, the image signal (000101) is sequentially input one bit at a time in synchronization with the rise of each of the pulses a1 to a6 of the read lock E, and as a result of being shifted, the address terminals of the ROM2 (AoyAt, As, As, A4 . As+As,
Assume that an image signal (0, 0, 0, 0, 0, 1, 0, 1) is given to A)).

Here, the shift direction of the shift register 1 is from the address terminal A7 of the ROM 2 to the address terminal AO.

Then, this and % address terminals A1 to A6 of ROM2.
An image signal (000010) to be reduced is given. Furthermore, the (0) that was at address terminal A7 in the initial state is shifted to address terminal Ao of ROM2.
Furthermore, a 1-bit image signal (1) after the image signal to be reduced is input to the address terminal At.

At this time, the output terminals of ROM2 (Qo, Qt, (h, Q
*.

From Q4), as can be seen from Table 3, the address (00
(00010) is output in response to (000101). Also, in synchronization with the rising edge of pulse a6 of read lock E, a carry! signal is sent from counter 4! is output as a high level, the load signal -iQ is output as active from the Nant gate 5 from the rising edge of the pulse a6 to the falling edge of the pulse a6. As a result, data (oooio) is loaded into the shift register 3. This data (00010) is the read lock E pulse b1~
It is shifted in the shift register 3 in synchronization with the rise of the pulses C2 to Cs of the shift clock signal C output from the OR gate 6 in synchronization with b. On the other hand, the readout circuit 10
takes the shift clock C′t-receiver and outputs the data (o
ooio) are read out sequentially.

Meanwhile, during this period, the shift register 1 receives the next six pulses in synchronization with the rise of each of the read lock pulses b1 to b-.
The video signal is input one bit at a time, and is shifted one bit at a time by a shift register 1. By shifting this 6-bit image signal, the ROM 2 is given an 8-bit image signal. At this time, the image signal applied to the address terminal Ao of the 1:ROM2 is the last 1-bit signal (0) of the previously reduced 6-bit signal (000010). Discarded ROM2 Atois terminal A
The picture signal selected at 7 is the first bit of the 6-bit picture signal to be reduced next time.

In this way, the address terminals Ao-A 7 of R,0M2
Since an 8-bit image signal is applied to the ROM2, the corresponding 5-bit data is output from the output terminals Qo to Q4 of the ROM2. Since the carry F is outputted from the counter 4 as a high level, the load signal G is outputted from the Nant gate 5 as active from the rising edge of the pulse b6 to the falling edge of the pulse b6. As a result, the shift register 3 is loaded with the 5-bit data output from the ROM 2. This data is shifted by the shift register 3 in synchronization with the rising edge of the shift clock C7 to C1 (1) of the shift clock 0 outputted from the OR gate 6 in synchronization with the pulses C1 to C11 of the read/read lock E. On the other hand, the readout circuit 10 receives the shift clock C and reads the above data in synchronization with the falling edge of pulses C6 to CI(+) of the shift clock C.

In this manner, in the tree embodiment, a reduced picture signal faithful to the original picture signal can be obtained by referring to 16 bits before and after each of the two signals that should originally be reduced.

In the above embodiment, a case has been described in which a 6-bit image signal is reduced to a 5-bit image signal, but there is no limit to the reduction ratio.

For example, to reduce a 3-bit signal to a 2-bit signal, a 5-bit input 2-bit output memory is used. At this time, instead of Table 1 explained as a conventional example,
A memory in which addresses and data are associated as shown in Table 4 is used. Of course, it is assumed that data is also stored at other addresses in this memory in accordance with the two precautions mentioned above.

If you have a memory piece like this in table 4, you can change it to ``7'' as a conventional example, or ``table 1'' in table 2, and ``5'' in table 2.

Table 5 As is clear from this Table 5, the 9-bit song shown in the 21st row of the 1st number, E', and the 4th bit, white (0).
is left as the third white (0) of the 6-bit image signal in the row of Q' column, and the white (0) is changed from the black (1) bit.
The changes to the hit and then black (1) bits are faithfully preserved. However, even in Table 5, there is not much improvement in just one row.

This means that of the 9-bit image signal shown in the 1st row of P'4%l in Table 5, the 3rd to 7th bits are added to the 5-bit image signal in the address grip p row of Table 4. This is because, in principle, it is impossible to leave the change from a black (1) bit to a white (0) bit, or the change from a white (0) bit to a black (1) bit.

Furthermore, in the above embodiment, the image signal is reduced by referring to 1 bit of the image signal before and after the image signal to be reduced. The image signal may also be reduced. For example, when reducing a 6-bit image signal to a 5-bit image signal, in order to refer to the 1-bit image signal before the image signal to be reduced, the configuration of the embodiment shown in FIG. Inside, ROM2 7
It is assumed that the bit input is 5 bit output, and the shift register 1
It is sufficient to shift the image signal by seven steps and start inputting the image signal from the read lock pulse a1. Furthermore, when reducing a 6-bit image signal to a 5-bit image signal, in order to refer to the 1-bit image signal after the image signal to be reduced, the configuration of the embodiment shown in FIG. Inside, ROM2 7
It is assumed that the bit input is 5 bit output, and the shift register 1
It's nice to have a 7-speed shift.

Furthermore, in the embodiment, only the case where the image signal to be reduced and reduced is given with a fixed number of bits has been explained, but for example, a series of both signals can be converted into both signals with a fixed number of bits in a fixed number of bits. The image signal may be reduced, and the last remaining few bits may be reduced to an image signal of the required number of bits by the same image signal reduction device. For example, in the embodiment shown in FIG. 1, assume that both signals with a number of bits not divisible by 6 bits are input, and a 4-pit image signal remains at the end. In this case, the remaining 4 bits are also input to the image signal reduction device in the same manner as the other image signals, and then, for example, a dummy image signal of white (0) bit is input, and 5 bits are output. And then I was fucked 5
Of the bit image signals, the circuit 10 may be configured to read both signals of the necessary number of bits.

〔Effect of the invention〕

As explained above, according to the present invention, in principle, the original picture signal changes from the black (1) bit to the white (0) bit, and from the white (0) bit to the black (1) bit. This change can remain, except in cases where the change cannot be left behind. Therefore, it is possible to reduce the image signal in a state closer to the original image signal, and the reduction performance in each type 1 can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of an image signal reduction device according to the method of the present invention, and FIG. 2 is a timing chart for explaining the operation of FIG. 1...Shift register (serial/parallel converter) 2...
...ROM (memory) 3...--Shift register (parallel-serial conversion section) 4...
...Counter 5...Nands gate (first logic gate) 6.
...OR gate (second logic gate) 7...
...Timing control unit 10-... Readout circuit agent Patent attorney Hon 1) Takashi

Claims (4)

[Claims] (1) A serial-to-parallel converter that converts the serially input binary image signal into parallel and outputs the A bit and G parts, and inputs the A-pit image signal output from the serial-to-parallel converter as an address. A memory that outputs the B-bit data stored in correspondence with this address, a parallel-to-serial converter that inputs the data to be outputted from the memory, converts it into serial data, and outputs it, a timing for loading the data loaded into the parallel-to-serial conversion section, a timing for outputting the data loaded to the parallel-to-serial conversion section from the parallel-to-serial conversion section, and a timing for reading out the data output from the parallel-to-serial conversion section as an image signal. and a timing control unit that controls the timing of the load, and transmits a load signal instructing the load timing to the parallel-to-serial conversion unit each time an image signal of A-1 bits or less is sequentially input to the serial-to-parallel conversion unit. An image signal reduction method characterized in that an image signal of A-1 bits or less is reduced to B bits by referring to at least one bit before or after it. (2) The timing control section converts both the A-2 bit signals by applying a load signal to the serial-parallel converting section every time the A-2 bit image signal is sequentially input to the serial-parallel converting section. B with reference to the previous 1 bit and the subsequent 1 bit.
Claimed pipe characterized in that it is reduced to a pit (
Image signal reduction method described in section 1). (3) The timing control section inputs the reading lock of the image signal given to the serial/parallel conversion section and outputs a carry for each predetermined bit below A-1 bits, and the timing control section outputs a carry from the counter. a first logical sum of the carry and the read lock, and outputs the result as a signal indicating the timing to output data from the parallel-to-serial converter and a signal indicating the timing to read the data output from the parallel-to-serial converter; and a second logic gate that generates and outputs a load signal from the carry output from the counter and the read lock. Image signal reduction method described. (4) A patent claim characterized in that the serial-parallel converter is a shift register that outputs the A-pit image signal in parallel, and the parallel-serial converter is a shift register that inputs B-bit data in parallel. Range of items (1) to (3)
) The image signal reduction method described in any of the above items.