JPS6065358A - Cache control system - Google Patents

Abstract

PURPOSE:To decide easily the validity or invalidity of TAG information without providing a valid bit by analyzing the address information corresponding to a non-resident area in the TAG information corresponding to the non-resident area. CONSTITUTION:The accesses are fed simultaneously to a cache memory 2 and a TAG memory 3 by upper bits #8-#15 and lower bits #16-#19 of an address register 10, respectively. Then ''0'' and ''1'' are added to the memories 2 and 3, respectively, at the head of 14 bits of lower addresses #16-#29 to obtain 15 bits. Then an access is fed to the memory 2. The prescribed read data of 4 bytes is outputted by a top bit from an upper resident area 21 and a lower non-resident area 22 when each head bit is ''0'' and ''1'', respectively. While the desired address bits #16-#26 are applied to the memory 3 from the register 10. Then the cache validity of the area 22 is confirmed when the address information #8-#15 contained in the read-out TAG information are coincident with the upper addresses #8-#15 of the register 10.

Description

[Detailed description of the invention] (1,) Technical field of the invention 13'J C1-: =
By making the parking area one-to-one with the main memory, the TAG information is not lost, and only the non-resident area has TA (Lj'7'j gear information). be.

(2) Prior Art and Problems Conventionally, a cache memory stores frequently used instructions or data in the main memory, and has i:j, li capabilities for directly accessing the main memory at high speed.

Data is exchanged between the cache memory and the main memory using TAG information. Due to the way microinstructions are used in the cache memory, if the frequently used areas are not placed on the cache, the performance will be greatly degraded.Therefore, the cache memory is divided into a resident area and a non-resident area. In this case, by creating a one-to-one correspondence between the cache memory and the main memory for the resident area, TAG ease (4 is unnecessary) can be achieved.
Hardware 1t is reduced by only reporting 'I'AGJj7 corresponding to non-resident areas.

However, in this case, the problem is how to determine whether or not an initial load has been performed from the main memory to the cache memory, and how to invalidate a certain area. This is dealt with by providing a valid pit in the TAG information to indicate whether it is valid or invalid. Note that the resident area is TA
A separate proposal has been made because G (does not have 'rr 114. However, I!I of the equivalent function without having a valid pit in the TA () information will reduce the hardware error. There is an effect, !1-.

(3) Purpose of the inventionPurpose of the invention In the cache control force formula that has only
This is achieved by providing a cache control method that can easily determine the effectiveness of H(,r).

(4) In order to achieve the invention (1), the cache management method (11) of the present invention is divided into a permanent area and an emergency area (1). By dividing the area and making the resident area correspond to the main memory, TAG information is provided only in the non-resident area without having TAG information. This method is characterized by determining the validity and thermal fluctuation of the 'I'AG information in the non-resident area by analyzing the address information corresponding to the non-resident area in the cache memory during the information phase.

(5) Examples of the invention t81 Figure 0 is a principle theory tyj diagram of Kien 1jrJ.

The figure shows an actual example of the distribution of the resident area 21 and non-resident area 22 in the cache memory 2, the configuration of the main memory 1 for sending and receiving data (move-in/move-out), and the 4n configuration of '1''AG3. be. That is, in the cache memory 2, the address (13-#l)
:15) 200+e ('#8-IN5 bit means all 0 in hexadecimal notation) corresponds to the resident area, and (41:8-IN5)'vODt6 corresponds to the non-resident area. and divide the distribution of both areas equally. Then, in hexadecimal notation, the address of main memory 1 “[][JO[]
641 (The byte area is not moved out after being initially loaded into the resident area 21 of the cache memory 2 and always exists on the cache memory.

Also, main memo v, 1 at l/s 1000i1-FFF
As for FFF, similarly to the conventional cache method or buffer method, the control η(11, to 64 defined in the non-resident area 22)](-f)'s /11i'(,1,...) is executed in units of 32 bytes. The data is moved in/moved out, and the υ address is confirmed between the main memory 1 and the keypad memory using the information in the TAG memory 6.

Here, in the conventional 1'AG memory, as mentioned above, '
1' Indicates whether AG is valid or invalid); I want to provide a lid pit, perform an initial load from main memory to cache memory 2, determine whether or not, and invalidate a certain block. However, in the present invention, as shown in h12 above, one side memory 2 is used as a permanent area and an emergency Hgpt.
This valid pit is removed by using the four columns of the address obtained from the f1 (9 components), which are equally divided into 1 (1 and 1 components).

)"The area loaded into the non-resident area is always at the address ('l!8-#H5)=01tnFF1s, and 0016 does not exist. Therefore, fJL]+i is written in the TAG11 information corresponding to the non-resident area. Non-resident '? in the excluded cache memory corresponds to 1 game (41: (3#H
5) If any one of =01u+FF+a is selected, XTA is detected by detecting a match with the address at the time of access.
G! The same effect can be obtained without providing a lid pit in the 'r'f phase.

FIG. 2 shows 41.
1] This is an explanatory diagram.

In the figure, the cache memory 2 is equally divided into a resident area 21 and a non-resident area 22, as explained in FIG. TAG memory 3 is non-resident area 2 of cache memory 2
The address information (#8-#15
). Conventionally, in addition to this, there was a valid pit indicating whether the corresponding block was valid or invalid, but this is removed in the present invention. Furthermore, P. .

P is paridipit.

For these cache memory 2 and TAG 3, address register 10's 3rd position pin) (#L8-#
15) and lower pits (#16-#29) at the same time. In other words, the upper address (4L8-111
5) into the area determination circuit 11, and ``=(DO)+o(t
If t8 to #15 are all 0), it is determined that it is a resident area,
~(U IJ ) +6<p8~1116 are not all 0), then non-'r:'r Q a"l "Q and "I"
U')'rl. Soshi-r 下rlk 7 トL/
The cache memory 2 is accessed by adding °υ'' to the beginning of the 14th bit of the bit (fl:16=I+29) for the former, and for 1?, set the bit by 4XJ to make it 15 bits. If it is "11", it may be the upper permanent area 21, or if it is "1", it may be -1 part of the non-resident area/iil or 2.
2 to output a predetermined 4-byte read return. On the other hand, the required ° from address register 10! , the address bits (#6-ll:26) are placed in the TAG memory B, and the address information (#t8-Yu15) in the TAG (Part 1, No. 1'14) read by access is stored in the address register. (If it matches i7' address (#l:8-1NS), non?lj'I!'I'p・il, 12i1
The validity of the 422 cache is ensured.

Then, the C1 area determination circuit 11 indicates that ("OOJ is detected k lI:? &J, cache in non-resident area 22 is invalid +"r).

(6) Effects of the Invention and More B)a) As explained above, according to the present invention, the address 17T information corresponding to the non-resident area in the cache memory can be obtained during the TAG information corresponding to the non-resident area in the cache memory, and the access By detecting a match between the address of the remote area and the address in the L'A () information, it is possible to easily determine whether the non-resident area is valid or invalid, without providing a phase add bit in the rAG 'li'j information. This helps to effectively reduce the AG memory 11-.

[Brief explanation of the drawing]

Figure 1 is a non-fire] λ9 theory j3+'Figure 1, 2n Figure 2 is implementation 15' of the present invention! This is an explanatory diagram of the J structure of l, in which ikl is the main memory, 2 is the cache memory, 21 is the resident area, 22 is the non-resident area, and 61 is the TAG memory.
is a block corresponding area, 10 is an address register, 11 is an area determination circuit, and 12t'' is a soft circuit. 111d' ``Degawa 1 person Fujitsu f1ζ type company sub-agent patent attorney 11 Saka Arrival Type beam 1 Figure 2

Claims (1)

[Claims] jl,:IL- allows 'I'A (1 information to be produced without being able to produce TAG only for non-'ho resident (i1'i
In addition to the cache I1i'Ju.11 method, the TAG information in the non-resident area is validated by analyzing the address information corresponding to the default area in the TAGA phase information corresponding to the non-resident area. A cache control method characterized by determining invalidity.