JPS6065367A - Interruption control circuit of integrated circuit - Google Patents

Interruption control circuit of integrated circuit

Info

Publication number
JPS6065367A
JPS6065367A JP58174989A JP17498983A JPS6065367A JP S6065367 A JPS6065367 A JP S6065367A JP 58174989 A JP58174989 A JP 58174989A JP 17498983 A JP17498983 A JP 17498983A JP S6065367 A JPS6065367 A JP S6065367A
Authority
JP
Japan
Prior art keywords
circuit
key
state
signal
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58174989A
Other languages
Japanese (ja)
Other versions
JPH0312751B2 (en
Inventor
Yoshikazu Nishiura
西浦 義万
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP58174989A priority Critical patent/JPS6065367A/en
Publication of JPS6065367A publication Critical patent/JPS6065367A/en
Publication of JPH0312751B2 publication Critical patent/JPH0312751B2/ja
Granted legal-status Critical Current

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  • Power Sources (AREA)
  • Calculators And Similar Devices (AREA)
  • Microcomputers (AREA)

Abstract

PURPOSE:To ensure the effective actuation of an IC by selecting the contents of input for start of an interruption according to the state set previously to an FF and forms an interruption controlling signal. CONSTITUTION:An IC1 has a stand-by mode where all circuits stop their operations excepting for a clock generator 4 and a liquid crystal display circuit 3. Then the stopped circuits are started again via a start control circuit 5 when an exclusive OR output obtained between key inputs K1-K5 applied from a gate circuit 7 and an output signal C of an FF6 is set at ''1''. The state of the FF6 is controlled by a program and set before a stand-by mode is set. Then a state ''1'' or ''0'' is decided for the IC1. In other words, a start mode is set in case the signal C is ''0'' and either one of inputs K1-K5 is set at ''1'' or in case the inputs K1-K5 are all set at ''0'' with the signal C set at ''1'' respectively.

Description

【発明の詳細な説明】 く技術分野〉 本発明は集積回路における割込み制御回路に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an interrupt control circuit in an integrated circuit.

〈従来技(+l、j > CMO5I・ラーシヌタは・1\゛1−1氏消費″市ツ
ノに1円することから、こ]1を用いて構IJy した
集積回路についても、殴罰を動作させている1jli間
におい−C低泊費′1F力の効果を損わないように、む
しろ′11L力消費の低減を図るための工夫が1−(み
られている。
〈Conventional technique (+l, j > CMO5I/Rashinuta is 1\゛1-1 Mr. consumption'' since it costs 1 yen to the city horn, so this] 1) The integrated circuit constructed using IJy can also be operated with punishment. In order not to impair the effect of the power consumption, rather than reducing the power consumption, efforts are being made to reduce the power consumption.

例えば集積回路で機詔を動作さぜる1祭、動(’Ij!
11間中にスタンドバイモードを設け、″IE卓用卓用
−1〜IL111111路ればこのスタンドバイモート
の期間には夕ロックゼ不レーク及び液晶表示回路を除い
て、集積回路に含まれるその他の回路部分の動作を停止
1させ、これによって、消費′11i、力の低減を図ろ
うとする回路動作が採られている。一般に集積回路を」
1記のようなスタンドバイモートにさぜる動作は命令に
よってイ′iわれ、山゛ヌタートはキー人力にJ2って
行われている。しかし、従来回路のようにキー人力をス
フ−1−信号とした場合には、通常キー操作の期間は非
常に不均一であり、集積回路が一−11,スタンドバイ
モート 1甲され続けている場合がしばしばあり、この場合には
ヌクートが川ることになってC I) U等は動作を5
続けることになり、消費’ILカの、I!;」;1人を
招いて所j91のII的を達+1x L、?’、)ない
といつ間;1℃がある。
For example, the first festival to operate a mechanism using an integrated circuit, the movement ('Ij!
If a stand-by mode is set up during the 11-day period, and if the ``IE desk-1~IL111111 path'' is set, during this stand-by mode, other components included in the integrated circuit, except for the evening lock and the liquid crystal display circuit, will be disabled. A circuit operation is adopted in which the operation of a circuit part is stopped, thereby reducing power consumption and power.In general, integrated circuits are used.
The operation of turning on the stand-by mode as described in item 1 is disabled by a command, and the turning operation is carried out manually. However, when the human key input is used as a signal as in the conventional circuit, the period of key operation is usually very uneven, and the integrated circuit continues to function as 1-11 and standby mode 1-1. There are often cases in which Nukut becomes a river and C I) U etc. perform the action 5.
I decided to continue, consuming 'IL power, I! ;”; Invited one person and achieved the II target of place j91 +1x L,? ',) How long does it take to be 1℃?

1−記のJ:うな間jIlflK苅して、他の方法とし
てキーの後縁バウンスをijl数するカウンタを設け、
キーのハウノノカウン1−をバー1−゛で行って計数イ
直が所定前に達する寸でその間集4;’i回路中のCI
)U等の大部分を停屯させておくことも行われている。
1-J: Unama jIlflKari, as another method, provide a counter that counts the trailing edge bounce of the key,
Perform the key count 1- with the bar 1-'', and when the count reaches the predetermined value, collect 4;'i CI in the circuit.
) U, etc., are also stationed for the most part.

しかしこの方法においてはバウンスカウントの時間が1
.’、I定され、停止期間を長びかせることによって6
11算処J111に支障をきたす惧れもある。
However, in this method, the bounce count time is 1
.. ', I is set, and by lengthening the stop period 6
There is also a risk that this may cause problems with the 11 calculation J111.

いす九においても、スクント−バイモードかラノヌクー
ト時等のような割込み起動に際して、効率的な副側1動
作が行われているとはいい難かった。
Even in ISUKU, it was difficult to say that the secondary side 1 operation was performed efficiently when an interrupt was activated, such as when in scunto-bi mode or ranonukuto.

〈発明の目的〉 本発明は上記従来の割込み制御回路の欠点を除去し、必
υ最小限の詩にだけ効率的に割込みを受けて動作を実イ
1することができる集積回路を提供する。
<Objective of the Invention> The present invention eliminates the drawbacks of the conventional interrupt control circuits described above and provides an integrated circuit that can efficiently receive interrupts and perform operations only when necessary.

〈−ノご him 1列〉 !1コ債回路として第1図に示す電4L用CMO5Iチ
ップマイクロコンピュータを乍げ、割込み原因トシてス
タン1−バイモートからのノ・ノート’、!? ??;
 ケて説明する。
<-nogo him 1st row>! The CMO5I chip microcomputer for electric 4L shown in Figure 1 is installed as a single bond circuit, and the interrupt source is the standby node from the standby mode! ? ? ? ;
Let me explain.

集積回路1には、この種の従来回路と同(5)JにCI
) U 2 、液晶表示回b′lj3、タロツクゼネレ
ータ4及びヌクート制御回路5が一体的に設けらノ′と
、更に命令やデータを記憶させるだめのメモリ回路(1
ン1示せず)等が設けられて、集積回路1が電卓として
機能し得るように各回路間がイ[」互に接続されている
。特に本実施例の集積回路におけるC PU2ば、割込
み制御のだめのフリップフロップ6を含んで構成されて
いる。該フリソプフロッ16の状態を表わす信号Cは、
キー人力に1〜に5が与えられたゲート回路7に与えら
れて、−4−記キー人)月く1〜に5と信号Cとのυ1
他的論坤和かとられ、ヌク−1−制御回路5への人力信
号が形成される。
The integrated circuit 1 has the same CI (5) J as this type of conventional circuit.
) U 2 , a liquid crystal display circuit b'lj 3, a tarot generator 4 and a control circuit 5 are integrally provided, and a memory circuit (1) for storing instructions and data is also provided.
1 (not shown), etc., and the circuits are interconnected so that the integrated circuit 1 can function as a calculator. In particular, the CPU 2 in the integrated circuit of this embodiment includes a flip-flop 6 for interrupt control. The signal C representing the state of the Frisopfloc 16 is:
5 is given to the key power from 1 to the gate circuit 7, and υ1 is given to the key power from 1 to 5 and the signal C is given to the gate circuit 7.
Alternative disjunctions are taken and a human input signal to the Nuku-1 control circuit 5 is formed.

上記集積回路はスタンドバイモードを持ち、このスタン
ドバイモードにおいては集積回路1はクロックゼネレー
タ4、液晶表示回路3を除き全ての回路が動作を停止す
る。スタンドバイモー1−ニlZJ’、 git令によ
り入り、スタンドハイモート′からの起動は、ケーl′
回路7からのキー人ノ月く1〜に、とフリノフ′フロノ
ソ°6の出力信号Cとのり1他的論即和出力か′】゛に
なったときにスクート制御回路5を介してハート′的に
行われる。
The integrated circuit has a standby mode, and in this standby mode, all circuits of the integrated circuit 1 except the clock generator 4 and the liquid crystal display circuit 3 stop operating. Stand by mode 1-ni lZJ', entered by git command, startup from stand high mode' is by case l'
When the key output from circuit 7 reaches 1~, and the output signal C of Furinoff'Fronoso°6 becomes 1, the output signal C is output from circuit 7. It is carried out according to

ここでオゴ記フリップフロップ6は状態がプロクラj・
で制n11]されるフリップフロップで、スタンドバイ
モ−1−゛に入る1)iJに設定され、次に集積1!4
1路をとのような状態にさせたいかによって状態゛1゛
°。
Here, the state of the flip-flop 6 is procl.
The flip-flop controlled by n11] enters the standby mode 1-1) is set to iJ, then integrated 1!4
The state ゛1゛° depends on whether you want the 1st road to be in the state like .

“′0゛が設定される。即ちフリップフロップの出力信
号Cが0゛°のときは、キー人力Kl〜Iり、のいずれ
か1つが1になったときにスフ−1−する。
"'0" is set. That is, when the output signal C of the flip-flop is 0°, when any one of the key inputs K1 to I becomes 1, the switch is set to 1.

まだ出力信号Cが“1゛のときには、キー人力に1〜に
5の1)てが“′0゛のときにスタートする。
When the output signal C is still "1", the operation starts when the keys 1 to 5 (1) are "'0".

第2図のフローチャー1・を用いて」1記実施例を更に
訂]111に説明する。
This will be explained in "Further Revised Embodiment 1" 111 using flowchart 1 in FIG.

今フリノゾフロノプ6がプロクラ11により出力信号C
として′0°゛に設定された状態でスタンドバイモード
′に入ったとする。これは集積回路がキー人力を7.+
iって待機している状態にあり、スタート(てよ−)て
に、〜に5のキー人勾妬1;jOいずノLか1つに人力
があfL Vl、C=Oの状1ルが判別さ、tlてCP
U 2は予め定められたスター1アドレスより動作を開
始する。集(「(」回路+71:キー人勾ルーチンを経
て人力されたキーに応じた71.it XI熱処理実1
1シフ、tfk晶表示のだめのヌテソゾを経てブl−1
クンノ・に」、リフリソフ゛フロップ6に11h力(j
i、lり、 Cとして′”J″。
Now, Furinozofronop 6 outputs signal C by Procra 11.
Assume that the camera enters standby mode with the camera set to '0°'. This is because integrated circuits are the key to human power.7. +
i is in a standby state, and at the start (teyo-), there is a key person of 5 in ~1; 1 le is determined, tlte CP
U2 starts its operation from a predetermined star 1 address. Collection ("(" circuit +71: 71.it XI heat treatment actual 1 according to the key pressed manually through the key press routine
1 shift, tfk crystal display no tesozo, blue l-1
``Kunno Ni'', 11h power (j
``J'' as i, lli, and C.

を設Wする。フリップフロップ6の状1:iis lr
・′”1゛に設定された後、CE N I)命令により
隋(、l7回路(1′:1スクンドバイモードに入る。
Set W. Flip-flop 6 state 1: IIS LR
After being set to '1', the CENI command enters the 17 circuit (1':1 scundby mode).

スタンド′ハイモー1−に入った集積回路において、い
ずれかのキーか」、だ押し続けられている場合、即ちキ
ー人力かある場合には、フリップフiffツブの出カイ
1−j号Cが“′]゛の状態にあるため集4’+”を回
路はその1ま荀機状態を保持し、キーが剛されて始めて
スフ−I−する3、キー人力信−号とフリップフロップ
の1ノ1他的論理和がスタンドバイモードから起動状態
にするだめのスタート信号・になっているため、キー人
カイ1−1号かlノえ続けられているならば、フリップ
フロップ6C1゜“1゛の状態にあるためスタート信号
はJ12.成されず、rIJ間状四に+)′7ゴる。キ
ーか!411ノしてヌター1゛すると、チ・、クリ/り
′写による:’、!li動角を1;力ぐ/こめのC−0
判別ステノーノ°のNO経路に図示したキーの後?l改
ハランス力・クンI・ルーチンを経てfi:!号Cヲ”
 o ”に設定した後CI’、 N P命令が実行され
る。
In the integrated circuit installed in the stand ``Hymo 1-'', if any key is kept pressed for a long time, that is, if the key is pressed manually, the output No. 1-j of the flip flop will be ``'' ] Since the circuit is in the state of 4'+', the circuit maintains the machine state, and only when the key is stiffened does it switch to 3, the key human power signal and the flip-flop 1. Since the other logical sum is the start signal for changing from standby mode to start-up state, if the key number 1-1 continues to be output, the flip-flop 6C1゜"1" Because the start signal is in the J12. state, the start signal is not generated and the rIJ interval is +)'7.When the key is pressed and the nut is pressed 1, the key is pressed and the key is pressed. li moving angle 1; C-0 of force/composition
After the key shown in the NO route of Discrimination Steno°? l Kai Haransu Riki Kun I Routine fi:! No.C wo”
CI', NP instruction is executed after setting to ``o''.

即ち後縁ハウンメガJ!li定1直に達してカウンタか
オーバーフローするとバウンスカウントを完了したもの
としてソリノグフ1−Iソゾ6をC=Oに設定し、最θ
Jのキーイ、5ち状、帳に戻る。キーのハ1タンヌカウ
ントが終了しなかった場合は、フリップフロップ6を0
−1の且丑に保持してCEND命令を実負し、山ひキー
人力がなくなるまで待(幾する。
In other words, the trailing edge Haun Mega J! When the li reaches constant 1 and the counter overflows, it is assumed that the bounce count has been completed, and the solinograph 1-I sozo 6 is set to C=O, and the maximum θ is
J's key, 5chi, return to the book. If the key count is not completed, flip-flop 6 is set to 0.
Hold it at -1 and execute the CEND command, then wait until the mountain key is exhausted.

このように本実施例の制御回路では、キーが押され続け
ても’4.’i機状態に留することかでき、消費′重力
を低減することができる。
In this way, in the control circuit of this embodiment, even if the key is kept pressed, '4. It is possible to remain in the aircraft state, and the consumption of gravity can be reduced.

上記実施例はスタンドバイモードからのスクートの:l
r制御について述べたが、消費重力か問題にならないよ
うな集積回路で、スタンドバイモードを態Cで1″′;
171iさ!した11、j1込みI!、j l’J (
・−)/Cめ0つ人ノ月1.餞とフリップフロップの出
力との4)11山1″白、、聞即J11 f IIIい
て1lr1.l 6111することかてきる1、〈力J
 果〉 以−1一本発明によノ′Lば、曲中な(1(1°)成を
1・j力11するのみて、集41′1回路のCPLJU
l、キー1.1」ち、キーハウンヌカウント力において
心安最小限の時だけ割込みを受けることになり、集(L
11回路として必’;33114J’/C動作さぜるこ
とかでき、消費電力の低1)・・’j、′:’;C’)
 4”l1点を&−J、しめ他の演算の処卯能力に全俗
か牛し、東(6回路を効率的に作動させることかできる
3、4.1ン1而のi’!−’i’l’ 7:1iな説
明ガ′51図は本発明による一実)j(ri、例の集積
回’trlの要部ブロック図、第2図は同実力温例の動
作を説明するだめのフローチャー1−である。、 1:集積回路、 2 : Cl” [1、3:フイタ晶
表小回路、 5ニスクーI・制御回路、 6:ツリノプ
フロノブ、7:ゲート回路、K、〜1り、:キー。
The above example shows how to scoot from standby mode: l
I mentioned r control, but with an integrated circuit where consumption gravity is not a problem, standby mode is set to 1''' in state C;
171i! 11, J1 included I! , j l'J (
・-)/Cme0jin no Tsuki 1. 4) 11 peaks 1'' white of the output and the output of the flip-flop.
As a result, according to the present invention, the CPLJU of the circuit 41'1 is calculated by applying the 1 (1 degree) configuration in the song to the 1 j force 11.
l, key 1.1'', the interrupt will be received only when the key Hound count power is at a minimum, and the collection (L
Required as 11 circuit; 33114J'/C operation, low power consumption 1)...'j,':';C')
4"l1 point &-J, and the ability to process other calculations is completely unknown, East (3, 4.1 n1 i'!- which can operate 6 circuits efficiently) 'i'l' 7:1 i explanation 51 Figure is a block diagram of the main part of the example integration circuit 'trl', Figure 2 explains the operation of the same actual temperature example. This is the flowchart 1-, 1: Integrated circuit, 2: Cl'' [1, 3: Fitter crystal table small circuit, 5 Nisku I control circuit, 6: Turinopflo knob, 7: Gate circuit, K, ~1 ri: key.

¥Jl 1ンI 色2図¥Jl 1n I color 2 diagram

Claims (1)

【特許請求の範囲】 1 rめ状■がプロクラム設定されるフリソプフfi 
7ゾを設け、割込みを起動するだめの人力の内容を」−
記フリップフロップに予め設定された状態によって選択
し、割込み制御信号を形成することを特徴とする集積(
i−i1路の割込み制御回路。 2 前記割込みを起動するだめの人力は複数のキー人力
であり、該複数のキー人力の内いずれか1つが真である
事象と、」−記イリ数のキー人力の全てがイロである。 11」象をフリップフロップの状態で選択することを特
徴とする集積回路の割込み制御回路。
[Claims] 1 Frisopf fi in which the r-shaped ■ is set as a program
7, and the content of the human power needed to activate the interrupt.''
an integrated circuit which selects according to a preset state of the flip-flop and forms an interrupt control signal;
Interrupt control circuit for i-i1 path. 2. The human power required to activate the interrupt is a plurality of key manpowers, and the event in which any one of the plurality of key manpowers is true; - All of the key manpowers of the number indicated are false. 11. An interrupt control circuit for an integrated circuit, characterized in that an interrupt control circuit selects an element in a flip-flop state.
JP58174989A 1983-09-20 1983-09-20 Interruption control circuit of integrated circuit Granted JPS6065367A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58174989A JPS6065367A (en) 1983-09-20 1983-09-20 Interruption control circuit of integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58174989A JPS6065367A (en) 1983-09-20 1983-09-20 Interruption control circuit of integrated circuit

Publications (2)

Publication Number Publication Date
JPS6065367A true JPS6065367A (en) 1985-04-15
JPH0312751B2 JPH0312751B2 (en) 1991-02-20

Family

ID=15988267

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58174989A Granted JPS6065367A (en) 1983-09-20 1983-09-20 Interruption control circuit of integrated circuit

Country Status (1)

Country Link
JP (1) JPS6065367A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012221136A (en) * 2011-04-07 2012-11-12 Shikoku Electric Power Co Inc Pulse measurement method and device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5741726A (en) * 1980-08-22 1982-03-09 Hitachi Ltd Process interruption input circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5741726A (en) * 1980-08-22 1982-03-09 Hitachi Ltd Process interruption input circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012221136A (en) * 2011-04-07 2012-11-12 Shikoku Electric Power Co Inc Pulse measurement method and device

Also Published As

Publication number Publication date
JPH0312751B2 (en) 1991-02-20

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