JPS606539B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a pattern of an integrated circuit using an irradiation beam exposure device such as an electron beam, and a method for manufacturing a semiconductor device based on the pattern forming method. It is.

To manufacture an integrated circuit, first a mask is manufactured to determine the diffusion position and electrode wiring position.

The above-mentioned mask is overlaid on the wafer on which the oxide film has been formed and the resist film has been formed, and optical exposure is performed to selectively convert the resist into a solid solution depending on whether or not the resist film is exposed to light. Then, the impurities are diffused from there. Furthermore, for the next process, the steps of oxide film formation, resist film formation, mask exposure, etching, and diffusion are repeated in the same manner as described above. As the pattern size of integrated circuits is required to become smaller, the conventional method of optical exposure using a mask corresponding to each process has a limit on the pattern size due to the diffraction effect of light. To solve this problem, it is essential to use an electron beam exposure device with a much shorter wavelength. When manufacturing integrated circuits using electron beam exposure equipment,
Since it is possible to electronically control the electron beam and directly irradiate the wafer, there is no need for subsequent mask manufacturing and mask alignment processes, but it is necessary to align the wafer within the electron beam equipment after diffusion. It is.

Furthermore, to specifically explain the steps of a standard manufacturing method for integrated circuits using an electron beam exposure device, first, a wafer with an oxide film and a resist film formed thereon is placed in the electron beam exposure device, and the wafer is placed in the electron beam exposure device. After creating a vacuum of about torr, pattern information stored on the magnetic tape or disk pack is edited and exposed to electron beams under the control of an electronic computer.

After drawing, the wafer is taken out, the resist film is dissolved, and the oxide film is etched and diffused. In the next process, the wafer with the oxide film formed and the resist film formed thereon is inserted into the electron beam device, and then etching, diffusion, etc. are repeated. During this repetitive process, alignment technology between each process is an important factor in producing integrated circuits. Alignment within an electron beam exposure system is usually performed by attaching a mark detection symbol to the wafer to detect positional information, and scanning the mark with the electron beam in the X-axis and Y-axis directions. The rotation correction and positional deviation are calculated based on the signal, and the beam deflection position is corrected. However, the alignment accuracy at this time is usually worse than the electron beam deflection position accuracy. Moreover, this alignment correction process is a time-consuming process. Furthermore, each time a wafer is inserted into an electron beam exposure system, it is necessary to perform high-vacuum treatment inside the lens barrel, operation of the electron beam, gain adjustment, astigmatism adjustment, etc., which requires a turnaround time for each process. The time becomes very long. Note that the following explanation will also be based on the case where an electron beam is used. The purpose of this invention is to improve the alignment accuracy between processes, which is the drawback mentioned above, to reduce the complexity of electron beam exposure operations,
An object of the present invention is to provide a method for manufacturing an integrated circuit, which aims to shorten the manufacturing process of the integrated circuit. The method for manufacturing an integrated circuit according to the present invention, compared to the conventional method in which one electron beam exposure drawing operation required pattern drawing for one process,
Patterns from multiple processes are drawn by changing the amount of electron beam irradiation for each process, and the difference in etching speed of the resist film caused by the difference in the amount of irradiation is utilized.
Its feature is that it distinguishes patterns among multiple processes.

More specifically, the amount of irradiation of the electron beam onto the wafer can be changed by changing the deflection frequency.

When a resist film is exposed to a mist beam irradiation amount above a certain value, the etching speed will vary depending on the irradiation amount, so it is possible to etch the resist film in stages depending on the relationship between the electron beam irradiation amount and etching time. be. Also,
The etching speed is determined by the mixing ratio of the developer, PMMA (polymethyl
methacrylate), Mada K (methyl isobutyl ketone), IPA (isopropyl alcohol)
By changing the ratio of , it is also possible to perform stepwise etching using the etching time as a parameter.
Hereinafter, the conventional example will first be explained with reference to FIGS. 1 to 3, and then the present invention will be explained.

FIG. 1 is a process diagram for explaining a conventional method of manufacturing a DSA-MOS transistor.

In FIG. 1, in order to form a p-type base region, impurity introduction windows 3 and 4 for forming source and drain regions are respectively closed in a first mask 2A for impurity introduction formed on a horizontal substrate 1. After that (FIG. 1a), a second mask 2B for impurity introduction is placed on the surface, and a window 5 is opened in the second mask 2B to include the window 3 for forming the source region.
(Figure 1b). A p-type impurity is introduced into the wedge-shaped semiconductor substrate 1 through this window 5 to form a base region 6, and the planar pattern of the base region 6 is determined by the pattern of the window 3. Next, the second mask 2B is removed to expose the windows 3 and 4, and n-type impurities are introduced to form a source region 7 and a drain region 8, respectively (FIG. 1c). Note that 9 is the gate Si02, 10 is the gate polysilicon, 2C is the first gate,
The second impurity introduction mask is an integrated Si02 film. In each of these steps, there is a step of opening windows 3 and 4, and a step of opening windows 5 and 5.
Different mask patterns are used in the process of opening the resist, and two masks, the first and second masks 2A and 28, are required for resist exposure, or two exposure steps are required for electron beam exposure. . Therefore, from the viewpoint of yield, it is inappropriate to make the distance between the edge of window 3 and the edge of window 5 smaller than the alignment accuracy in these two exposure steps, and in practice, a sufficient margin is provided. . However, since one end of the window 5 needs to be on the gate polysilicon 10, there are the following difficulties. Edge E of window 3 formed in a part of first mask 2A consisting of gate polysilicon 10 and gate Si029
, and the edge E2 of the window 5 on the gate polysilicon is D.
Assuming that the gate length is L, the edge E2 of the window 5 needs to be definitely on the gate polysilicon 10, so please note that
D, it must be ≦LD. Therefore, 2 SL
Therefore, the gate length L is limited to a minimum of 21, that is, twice the alignment accuracy. A conventional example that eliminates the above drawbacks will be explained with reference to FIG.

FIG. 2 is a diagram showing the amount of electron beam irradiation and the state of stepwise pattern etching.

The x axis is the position coordinate of the figure, and the Y axis is the beam irradiation amount (dose).
It is. 1 and 14 are curves of the irradiation amount for patterns P and P4, respectively. At the etching time, pattern P4 disappears, and at etching time, the pattern P
, are removed, and at etching time t3, patterns P2 and P3 are removed.

Therefore, pattern P4 can be treated as a separate layer from patterns P, to P3, and pattern P can be treated as a layer separate from patterns P2 and P3.
This means that it can be treated as a separate layer from layer 3. P
', ~P'4 indicate the progress of etching of the resist film for patterns P, ~P4, respectively, at the time of etching time t.

P'4 is in a completely empty state. Figure 3 a to e are the second
It is a process diagram when the method of the figure is applied to the manufacturing method of a DSA-MOS transistor.

First, as shown in FIG. 3a, Si0
2, a layer 13 made of a high-melting point metal such as Mo or W, and resist films 20, 21, 22, 23 (these resist films are the same before exposure, but considering what will happen after exposure) The resist film 20 is not exposed to the electron beam, the resist film 21 is exposed to a low amount of light, the resist film 22 is exposed to a medium amount of light, and the resist film 23 is exposed to a high amount of light (also given a different number). , the exposed resist film is indicated by a dash in the code). Next, as shown in FIG. 3B, the resist film 23 exposed to a high amount of light is developed and removed to form an etching window 17. Next, layers 13 and 12 are sequentially removed by plasma etching or the like to expose the surface S of m-type semiconductor substrate 11, and p-type impurities are introduced by ion implantation to form p-type base region 14. Next, as shown in FIG. 3c, the resist film 22' that has been exposed to a medium amount of light is developed and removed to form an etching window 18. Next, layer 1
3 and 12 are sequentially etched away to form a medium-sized semiconductor substrate 11.
The surface S2 of the etching window 1 is exposed, and the n-type impurity is removed from the etching window 1.
7. m-type semiconductor substrate 1 by ion implantation through 18
1 to form an n+ type source region 15 and an n+ type drain region 16, respectively. Next, as shown in FIG. 3d, the resist film 21' exposed at a low dose is removed, and the unnecessary layer
Remove 3. Next, as shown in FIG. 3e, the non-exposed resist film 20 is removed, and then a thermal process such as annealing is performed. As described above, the exposure process for forming impurity introduction holes for forming the base region can be performed at the same time as the exposure process for forming impurity introduction holes for forming the n+ type source region 15 and nx type drain region 16. Registration accuracy can remove minimum gate length limitations. In the above case, if there is a heat step between each process, the resist film cannot be applied as it is because it is generally weak to heat.

Therefore, in this invention, by using a multilayer film made of two or more layers of heat-resistant materials, differences in etching speed of the resist film caused by the magnitude of the electron beam irradiation amount to the resist film are transferred to the multilayer film and recorded. , which are sequentially used in each step including the subsequent heat treatment step. Examples of the present invention will be described below. Figure 4 a~
e is a process diagram showing one embodiment of this invention, in which each element is made of Si
This is a method of obtaining two steps by one electron beam exposure: a step of dividing the MOS transistor by 02, and a positioning step including two steps of determining the impurity introduction positions of the source and drain of the MOS transistor. In FIG. 4a, films 32 and 33 made of a heat-resistant material are formed in a multilayer structure on a wafer 31, and a resist layer 34 is formed thereon, and this resist layer 34 is similar to the previous embodiment. Resist layers 34A and 34B having two thicknesses are formed by performing two-stage exposure and first-stage etching.

In FIG. 4b, both films 32 and 33 are etched using the pattern of this thinner resist layer 34B.

Next, as shown in FIG. 4c, the etching of the resist layer 34 is continued until only the thicker resist layer 34A remains.

Next, as shown in FIG. 4d, a film 33 is formed by etching using the pattern formed by this thick resist layer 34A.

Thereafter, a thermal oxidation process is performed on the wafer 31 to form a thermal oxide film 35 on the portions not covered by the film 32. Next, as shown in FIG. 4e, the film 32 is
By performing etching and performing ion implantation or impurity diffusion according to the pattern of the films 32 and 33,
Impurities are introduced into the source region 36 and drain region 37.

Here, the film 32 is made of molybdenum, silicon nitride, or the like, and the film 33 is made of a heat-resistant material such as aluminum oxide or Si02.

In this way, each pattern for two processes including a thermal process is formed by a multilayer film made of a heat-resistant material by one electron beam exposure.

Note that this invention uses an electron beam as the irradiation beam, as well as an electron beam.
It is also possible to use ultraviolet light or other light rays or radiation.

As explained in detail above, this invention takes advantage of the fact that the etching speed of the resist film varies depending on the irradiation dose of the irradiation beam, records the pattern in each process on a multilayer film made of heat-resistant material, and then performs a heat treatment process. Since it is used as a mask for sequentially performing necessary processes including the above, it has the advantage of being able to perform processes at high temperatures that cannot be withstood by a resist film.

[Brief explanation of the drawing]

1A to 1C are process diagrams for explaining a conventional method of manufacturing a DSA-MOS transistor, and FIGS. 2A to 2C are electronic diagrams for explaining a conventional example that improves the drawbacks of the conventional example in FIG. Figures 3a to 3e show the beam irradiation amount and the state of stepwise pattern etching.
FIGS. 4a to 4e are process diagrams showing an embodiment of the present invention when applied to a method for manufacturing an S transistor. In the figure, 12 is a layer made of Si02, 13 is a layer made of a high melting point metal, 14 is a p-type base region, 15 is an n+ type source region, 16 is an n+ type drain region, 17, 18 are etching windows, 20, 21, 2
2 and 23 are resist films, 31 is a wafer, 32 and 33 are films made of a heat-resistant material, and 34, 34A, and 34B are resist layers. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. In a semiconductor device manufacturing method in which a wafer is subjected to processing including a heat treatment step using masks with different patterns for each of a plurality of steps, the wafer is provided with a multilayer film made of two or more layers of heat-resistant material, and further A resist film is formed on the resist film, and the resist film is irradiated with an irradiation beam while changing the irradiation amount for each pattern required for each step of a plurality of steps to simultaneously draw patterns of the plurality of steps on the resist film, and the irradiation beam is applied to the resist film. Patterns corresponding to each process are recorded on the multilayer film made of the heat-resistant material by utilizing the difference in etching speed of the resist film caused by the magnitude of the beam irradiation amount to the resist film, and each pattern of the multilayer film is recorded. 1. A method of manufacturing a semiconductor device, comprising sequentially performing necessary treatments including a heat treatment step using the mask as a mask.