JPS6066384A - Memory control circuit - Google Patents

Abstract

PURPOSE:To initialize all cells by the writing time of one bit by constituting an address control part of a memory by a 2 input NOR circuit. CONSTITUTION:Address signals Ao-Ai are inputted to one input of the 2 input NOR circuits 7-9 and a reset signal RST is inputted to the other input. When the signal RST is logical ''0'', inversion signals Ao-Ai are outputted respectively from the outputs of the NOR circuits 7-9. The outputs of the 2nd NOR circuits are inputted to one inputs of 2-input NOR circuits 10-12 respectively and the reset signal RST is connected to the other inputs of the NOR circuits 10- 12. When the signal RST is logical ''0'', the forward conversion signals Ao'- Ai' of the signals Ao-Ai are outputted from the NOR circuits 10-12. Namely, the whole cells are initialized. The reset signal RST obtains logical ''1'' to similarly initialyze the cell. The writing time of 1 bit, initialyzes on eutire cell so that these cells can by used for a memory control circuit effectively.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory control circuit, and more particularly to an address control circuit that drives all address decoder circuits.

Conventionally, to initialize a memory circuit, it is necessary to specify addresses sequentially and write data. In a memory circuit with memory cells of 2 (i + 4) bits (where i is a positive integer), 1 bit of data must be written. If the time required to write all the data is expressed as seconds, it will take kX 2 (1+s) seconds.

A conventional example will be explained using FIG. Address signal Ao~
AI is connected to the input of inverter circuits 1-3, respectively. The output of the inverter circuits 1 to 3 is Ao%A, respectively.
It generates inverted 100 numbers A0 to Ai of i, and is connected to the inputs of inverter circuits 4 to 6. The inverter circuits 4 to 6
is the inverted signal of A O−A 4, that is, Ao%Ai
Normal rotation signals Ao' to A, / are generated. For example, when logic "0" is input to address signal Ao, An becomes logic "1".
, Ao' becomes logic "0".Address signal Δo -
Inverted signals A0 to Ai and normal rotation signal A generated from AI
By inputting o/ to Ar in an appropriate combination to the address decoder circuit, one address signal can specify 2 to the power of (i+1) memory cells.

For example, memory cell address 1 is (A0/, A1/...A
1/).

2 Yl; The ground becomes (Ao, A,',...Ai').

By the way, in the conventional example described above, it is not possible to select one memory cell at a time for the combinations A, o to Ai, and in order to initialize all cells, it is necessary to select kx2(i+4).
It takes seconds.

The invention was made with this point in mind, and the reset signal is input! When '1-', all memory cells have logic ''
The object of the present invention is to provide a memory control capable of writing data of 0'' or logic +111+ in a writing time of one pit.

According to the invention, in the memory control path 1q, which includes all address decoder circuits of the memory and an address control circuit to drive, all of the address control circuits are configured as two manual NOR circuits, and one input of the NOR circuit has an address input. A memory control circuit is obtained which is characterized in that all the control signal lines are connected to the other input, and all cells are initialized in one pit write time when the control signal is input.

Next, the present invention will be explained in detail using the drawings. FIG. 2 shows an embodiment of the invention.

The uninvented embodiment shown in FIG. 2 is composed of a two-man power NOR circuit, and one of the two man-power N (JR circuits 7 to 9 is input with an address signal ~Ai, and the other input is connected to an address signal. The reset signal R8T is manually input.Reset signal R
When ST is logic "0", the two-man NOR circuit 7
The address signal A is applied to the Uj force of .about.9, respectively. -Ai
The inverted signal A. -Ai is output. The two-manpower N (JR
The output of the circuit is further 2 human power I'J OB circuits 10 to 12
, and the reset signal R8T is connected to the other human power of the circuits 10 to 12. Similarly, when the reset signal R8T is logic "0", the two human power N (to the output of the JR circuits 10 to 12) is connected to the reset signal R8T. is the inverted signal of Ao%A4, that is, the normal signal N.' to Ni' of Ao%Ai is output.

When the reset signal R8'l' is logic "On",
The non-rushing flow example provides the same functionality as the conventional example shown in Figure 1.

Next, when the reset signal ST becomes logic ``1'', the 2
The output of the human-powered NOR circuit is all logic "o", and by configuring the address decoder circuit entirely with NOR, type logic, the output of the decoder is X. -Xn are all ``1'', and all cells are selected. When the reset signals R and 8'I' are at logic ``1'', the entire memory circuit is set to write mode, and the write data is set to logic ``0'' or logic ``1'', thereby adding data. is written to all cells. Therefore, the reset signal R8
When T is logic 61', the initial write time of all cells is 1ts in seconds for one pin write time.

FIG. 3 is an embodiment showing the structure of a memory using the invention. The address control circuit 13 has an address signal Ao-A.
i and the reset signal R8'r are input, and the control circuit 1
The outputs of the control circuit 13 are connected to address decoder circuits 14 to 16, and the outputs of the control circuit 13 are connected to the decoder circuits in a combination based on a binary coded 1ltI number. For example, the address decoder circuit 14 (Ao', Al', . . .
Ai/), the address signals are all logic “OI
+ When the reset signal R8T is logic “0”,
The decoder circuit 14 is selected and the decoder circuit 14
The output of the decoder circuit becomes logic 11". At this time, the other decoder circuits 15 and 16 become non-selected, and their output becomes logic "o". When the reset signal 1 also becomes ST becomes logic "1", the decoder circuit 14 to 16 are all selected, and all memory cells are selected.

As explained above, the non-invention is to change the memory address control section to 2.
By using a manual NOR circuit, all cells can be initialized in a 1-bit write time, which is effective when used in a memory control circuit.

[Brief explanation of drawings]

FIG. 1 is a logic circuit diagram showing a conventional example of an address control section.
FIG. 2 is a logic circuit diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram showing the entire configuration of a memory using undeveloped memory. Explanation of symbols 1 to 6... Inverter circuit, 7 to 12...
- 2 manual NO, R, circuits, 13...address control circuit, 14-16...address decoder circuit, 17...memory cell. Atsushi / Figure zs7 爲? Figure F'S7 13 Figure

Claims (1)

[Claims] An address control circuit for driving an address decoder circuit of the memory.The memory control circuit is composed of a two-way NOR circuit, and each address line is connected to one input of the NOR circuit, and the other is connected to the memory control circuit. 1. A memory control circuit, wherein a control signal line is connected to an input of the memory circuit, and all cells of the memory circuit are initialized in one bit write time.