JPS6068448A - Common method control system of multicomputer system - Google Patents

Abstract

PURPOSE:To attain the control of resources with software by locking the mutual relation of data to prevent fetching of these data via an internal bus in case a master device is processing one of data stored in a common memory. CONSTITUTION:A master device 20 outputs a bus busy signal 13 to occuply a system bus 9, then transmits a memory drive signal 8 and an address signal to obtin desired data from a common memory 5. A clock signal generating circuit 14 receives signals 13 and 8 to output a signal 15 to prevent a CPU1 from accessing to the memory 5 via an internal bus 3 and locks the accesses fed to a common memory access control circuit 7. The circuit 7 outputs a common memory access signal 6 to the memory 5 to erase the signal 8. Thus the device 20 receives data. The signal 13 is outputted continuously while the device 20 is processing data. At the same time, the lock signal 15 is maintained.

Description

[Detailed Description of the Invention] [Technical field to which the invention pertains] A computer is provided in a computer connected to a system bus including a plurality of computers, and is accessed from the computer via the internal bus as well as from other computers. The present invention relates to a method for controlling access to data shared within a system stored in a common memory configured as a dual port memory so as to be accessible via the system bus.

[Prior art and its problems]

FIG. 1 shows a conventional configuration of an information processing system having a shared memory consisting of this type of dual port memory. In FIG. 1, ■, 17 is a central processing unit (CPU), 2
, 3 is an internal bus, 4 is an internal bus memory access signal, 5
is a common memory consisting of dual port memory, 6 is a memory access signal, 7 is a common memory access circuit, 8 is a memory drive signal, 9 is a system bus, 11.12 is a register, 16 is a normal memory, 18.19 is an input Shows the output circuit. Master devices (computers) used in such information processing systems include those that use a common memory 5, as shown at 10, and those that use a normal memory 16, as shown at 20. , the master devices 30, 40 are also configured like the mask devices 10 and 20.

In such an information processing/system, the shared memory 5 in the master device 10 is connected to the internal bus 3 and the system bus 9.
Since there may be conflicting accesses from multiple users, a prior access priority system is used. In other words, Figure 2 (5)
As shown in the time chart, during a period T1 in which the common memory 5 is accessed by the internal bus memory access signal 4 and the memory access signal 6 is output, the system bus 9 is Even if an attempt is made to access the common memory 5 after the memory drive 2 type signal 8 is issued from the side, the access from the system bus 9 is made to wait for a period T2 until the access from the internal bus 3 is completed. Conversely, if the common memory 5 is accessed by the memory drive signal 8 from the system bus 9 and an attempt is made to access it by the access signal 4 from the internal bus 9 during the period T3 when the memory access signal 6 is output, the access from the system bus 9 is not possible. During the period T3 until the end, access from the internal bus 3 is made to wait.

Such a prior access priority method is used because when access from one of the internal bus 3 and system bus 9 is completed, access from the other bus becomes possible.
As shown in Figure (Bl), periods A and C in which the common memory 5 is accessed by the memory drive signal 8 from the system bus 9 cannot be accessed by the internal bus memory access signal 4 from the internal bus 3; It is possible to access the memory 5 by means of an internal bus memory access signal 4.

By the way, if there is data that is shared within the system in the common memory 5, and there is some data (hereinafter referred to as resources) that has a correlation with each other, priority is given to early access as described above. If it is just a method, if one of the data is read and processed by some master device in period 4 and returns again in period C, while the data is being processed outside. If the central processing unit 1 reads and processes related data other than the relevant data during period B, the correlation may become incorrect.

Conventionally, when data having this kind of correlation is accessed from many mask devices and resource management is performed, a normal memory is directly connected to the system bus 9, and the mask devices access the memory as necessary. is normal. In this case, by sending a bus busy signal on the system bus to inform other mask devices that one mask device is using the system bus and prohibiting use from other master devices, the memory is always stored in one mask device. There is no problem because it is only accessed by.

However, if the configuration is such that the common memory 5 in FIG. 1 can be accessed from both the internal bus 3 and the system bus 9, one master device may be using the system bus 9 and output a bus busy signal. However, since access is possible from the internal bus 3, a situation may occur where correlated data is used multiple times and the correlation becomes out of order, as described above.

In order to solve such problems, the conventional technology uses a central processing unit 1 as shown in 11.12 in FIG.
Write only to other master devices from 20.30.4
A register 12 that can only be read from 0 and a register 11 that has the opposite relationship are prepared. Before the central processing unit 1 uses the resource, it reads the register 11 and determines whether the resource can be used. If the resource can be used, the register 12 is read-only. 12 to prohibit the use of the resources of the master device 20. In the opposite case, the master device 20 first reads the register 12 and sets the register 11 after making a determination.

However, in this method, each time a resource is used, the register 11,
Otherwise, it is necessary to read and write 12, which increases the burden on the shiftware. Furthermore, it is necessary to control so that the master device 2o does not read the register 12 while the central processing unit 1 is setting the register 12, and to prevent the central processing unit 1 from reading the register 11 while the master device 2o is setting the register 11. The disadvantage is that it requires additional hardware that slightly slows down the timing.

[Purpose of the invention]

The present invention addresses the above-mentioned circumstances, and in an information processing system having a common memory, minimizes the number of accesses, reduces the burden on software, and at the same time creates a common memory where two master devices have mutual relationships. While one piece of data is being processed, related data is locked via the internal bus, thereby eliminating the shortcomings of the data format common memory access method and using simple hardware. The purpose of this invention is to provide an access method that enables software-based resource management through configuration.

[Key points of the invention]

The present invention is provided in a computer connected to a system bus including a plurality of computers, and is accessible not only from the computer via the internal bus but also from other computers via the system bus. In a power formula for controlling access to data shared within a system stored in a common memory configured as a dual-port memory, after reading common data in the common memory from the other computer, the computer The present invention is characterized in that access to the common memory from the internal bus side is prohibited during a period when a busy signal is output to the system bus.

That is, in the present invention, even when this common memory is not accessed from the system bus side, after the memory drive signal is output from the system bus side, while the bus busy signal is continuously output, the bus inside the device is At the same time, this was achieved by using existing signals on the system bus and simple hardware additions, without preparing any special signals for this purpose.

[Embodiments of the invention]

FIG. 3 shows a block diagram constructed using the present invention. In FIG. 3, the same components as in FIG. 1 are indicated by the same reference numerals. To explain this in comparison with the configuration diagram according to the prior art shown in FIG. 1, according to the present invention, a lock signal generation circuit 14 is newly added to the master device 10. becomes unnecessary.

According to the present invention, the memory drive signal 8 is transferred to the lock signal generation circuit 1 without directly entering the common memory access control circuit 7.
4, and the lock signal generating circuit 14 is also configured to receive a bus busy signal 13. A circuit example of the lock signal generation circuit 14 is shown in FIG. When the memory drive signal 8 is output from the system bus 9, the 5-R7 flip-flop 22 is set and the memory lock signal 15 is output.

In other words, when the memory drive signal 8 becomes 10", NOT
Through the circuit 21, its output becomes "1". Therefore, the input to the S terminal of the 7-lip flop 22 changes from 0'' to 1''. On the other hand, at this time, the R terminal changes from @1m to "0#" because the bus busy signal 13 is input.As a result, the output Q of the 7 lip-flop 22 changes from 1# to "0", and the lock signal 15 changes to 0#. It is added to the memory access control circuit 7.Then, the memory drive signal 8 becomes "1#", the output of the NOT circuit 21 becomes OH,
Even if the input to the S terminal changes to 0'', the output Q of the flip 70 knob 22 remains at °'0# as long as the bus busy signal 13 is mOr+.Thus, when the bus busy signal 13 becomes 1#, the S terminal Since the input of the hole terminal is changed to 0# and the input of the hole terminal is ``1#, flip 70 knob 22
The output Q changes to l#, and the lock signal 15 disappears, returning to the original state.

In such a configuration, assuming that the external master device 20 accesses the common memory 5 and the mask device 20 processes the data, the master device 20 first issues the bus busy signal 13 to monopolize the system bus 9, and then The memory drive 2 outputs a type signal 8 and an address signal to take necessary data from the common memory 5. The lock signal generation circuit 14 outputs a memory lock signal 15 to prevent the central processing unit 1 from accessing the common memory 5 via the internal bus 3 under the condition that the bus busy signal 13 and the memory drive signal 8 are output. Access from other sources than the access control circuit 7 is locked. At the same time, the common memory access control circuit 7 outputs the common memory access signal 6. When the common memory access signal 6 is output and access is performed, the memory drive signal 8 disappears and the master device 20 receives the data. While the data is being processed in the master device 20, the busy signal 13 is continuously output. This causes the lock signal 15
is output while the bus busy signal 13 is output. Therefore, access to the common memory 5 from the central processing unit 1 is locked and other master devices 30, 40
Access to the common memory 5 from the system bus 9
is not performed because it is exclusive to the master device 20. The processed data is again written to the common memory 5 by the memory drive signal 8 and address signal. When the writing is completed, the writing memory drive signal 8 and the bus busy signal 13 disappear, so the lock signal 1
5 also disappears. This will return you to the initial state. When the central processing unit 1 accesses the common memory 5, it outputs the internal bus memory access signal 4, and the common memory access circuit 7
A memory access signal 6 is issued to retrieve data. During this time, the common memory access control circuit 7 cannot be used by others, so the others are locked.

FIG. 5 is a time chart of the embodiment of the present invention shown in FIG. As long as the bus busy signal 13 remains, the memory lock signal 15 is output and the stub vice 20
This shows an autumn situation in which the other central processing units 1 cannot access the common memory 5 until the processing on the other side is completed. That is,
When the memory drive signal 8 from the mask device 20 is used during the MD period, the common memory access signal 6 becomes 20.
During the period R, data is read by the master computer 20. During this time, even if the memory access signal 4 from the central processing unit 1 is in the MA period, the lock signal 15 is output during the BB8Y period when the bus busy signal 13 is output from the mask device 20, so unless this disappears, memory access will not be possible. Signal 4 is not valid and data enters central processing unit 1 starting from period 10 of common memory access signal 6 after period BBSY ends.

〔Effect of the invention〕

According to this invention, since the memory lock signal is created by combining the bus in use signal and the memory drive signal, even if the memory drive signal drops, access to the common memory from the internal bus side is suspended, and the software-based system resources can be managed correctly. In addition, there is no need to prepare a special signal for locking the memory on the system bus, so the system bus itself can be used as is, and only a small amount of new hardware needs to be added. Therefore, a new type of information processing system has been realized by establishing a simple and reliable control method for dual-port common memory with a light burden on software.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a conventional system, FIG. 2 is a time chart of the system shown in FIG. 1, FIG. 3 is a configuration diagram of a system as an embodiment of the present invention, and FIG. 4 is a memory according to the present invention. The circuit diagram of the lock signal generation circuit, vJs diagram, is a time chart of the system shown in FIG. 10.20, 30.40... Computer (master deno (chair), 1, 17... Central processing unit, 5... Common memo +) <f Yualhout type), 9... System node,
3... Internal bus, 13... Bus busy signal, 14...
. . . Lock signal generation circuit, 7 . . . Common memory access control circuit, 8 . . . Memory drive signal. Representative Patent Attorney Yamaguchi

Claims (1)

[Claims] l) Provided in a computer connected to a system bus including a plurality of computers, and accessed from the computer via the internal bus, as well as from other computers via the system bus. In a system for controlling access to data shared within a system stored in a common memory configured as an accessible unitary boat memory, after the computer reads the common data in the common memory,
A common memory control method for a plurality of computer systems, characterized in that access to the common memory from an internal bus side is prohibited during a period when the computer is outputting a bus busy signal to the system bus. 2) In the common memory control method for a multiple computer system as set forth in claim 1, the combination of a bus busy signal and a memory drive signal for inputting and outputting data from memory prevents access from a computer other than the computer in the process of accessing. A common memory control method for a multiple computer system, characterized in that the system is configured to generate a memory lock signal to stop the computer system.