JPS6068484U - Impulse test equipment - Google Patents
Impulse test equipmentInfo
- Publication number
- JPS6068484U JPS6068484U JP16077983U JP16077983U JPS6068484U JP S6068484 U JPS6068484 U JP S6068484U JP 16077983 U JP16077983 U JP 16077983U JP 16077983 U JP16077983 U JP 16077983U JP S6068484 U JPS6068484 U JP S6068484U
- Authority
- JP
- Japan
- Prior art keywords
- impulse test
- fet
- test equipment
- impulse
- power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Tests Of Electronic Circuits (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図および第２図は従来例に係るインパルス試験装置
を構成する回路図、第３図は本考案の一実施例に係るイ
ンパルス試験装置を構成する回路図、第４図は本考案の
他の実施例に係るインパルス試験装置を構成する回路図
である。
１１・・・・・・直流電源、１２・・・・・・ＭＯＳ−
ＦＥＴ。1 and 2 are circuit diagrams configuring an impulse test device according to a conventional example, FIG. 3 is a circuit diagram configuring an impulse test device according to an embodiment of the present invention, and FIG. 4 is a circuit diagram configuring an impulse test device according to an embodiment of the present invention. FIG. 2 is a circuit diagram configuring an impulse test device according to an embodiment of the present invention. 11...DC power supply, 12...MOS-
FET.
Claims (1)
、該ＭＯ５−ＦＥＴと直流電源および被試験素子をそれ
ぞれ直列に接続するとともに、前記ＭＯ３−ＦＥＴの絶
縁ゲートに制御信号発生回路を接続した回路構成からな
ることを特徴としたインパルス試験装置。A circuit configuration in which a power MO5-FET is used as a load current control element, the MO5-FET is connected in series with a DC power source, and the device under test, and a control signal generation circuit is connected to the insulated gate of the MO3-FET. An impulse test device characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16077983U JPS6068484U (en) | 1983-10-17 | 1983-10-17 | Impulse test equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16077983U JPS6068484U (en) | 1983-10-17 | 1983-10-17 | Impulse test equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6068484U true JPS6068484U (en) | 1985-05-15 |
Family
ID=30353534
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16077983U Pending JPS6068484U (en) | 1983-10-17 | 1983-10-17 | Impulse test equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6068484U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5530211A (en) * | 1978-08-25 | 1980-03-04 | Hitachi Ltd | Switching circuit |
-
1983
- 1983-10-17 JP JP16077983U patent/JPS6068484U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5530211A (en) * | 1978-08-25 | 1980-03-04 | Hitachi Ltd | Switching circuit |
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