JPS6068652A - Manufacture of semiconductor element - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing semiconductor devices, particularly high frequency transistors.

Generally, high-frequency semiconductor devices require extremely fine pattern designs in order to improve high-frequency characteristics. In particular, to improve the noise characteristics, it is necessary to form the emitter-base junction extremely shallow, raise the cutoff frequency fT, and reduce the base resistance. Therefore, in general, the emitter shape is miniaturized and the emitter is made smaller.

The distance of the base contact hole is reduced @1st
A conventional method for manufacturing high-frequency transistors will be briefly explained using figures. After forming a base region 2 on a silicon substrate 1 as shown in FIG. 1a), it is covered with an insulating layer 3, and then, as shown in FIG. is formed extremely finely. Thereafter, as shown in Figure C), an emitter layer 6 is formed by impurity diffusion or ion implantation through the emitter hole 4, and a base contact hole 5 is formed as close as possible to the emitter hole 4. Ta. However, commonly available photoetching methods are currently limited by the wavelength of light, and the minimum size is 1 μm.
The limit is approximately m, and there is also a limit to the mask positioning accuracy. Therefore, the limit for the emitter hole 40 dimension in Figure 1 b) is about 1 μm, and the distance between the emitter hole 4 and the base contact hole 5 in Figure 1 C) was also required to be 1 μm or more. This has been a bottleneck in obtaining the noise characteristics of transistor elements.

The present invention provides a method for manufacturing a semiconductor device that eliminates the above drawbacks and further improves noise characteristics.

The method of manufacturing a semiconductor device according to the present invention involves forming a thin layer of impurity-containing polysilicon directly on a base region, leaving the impurity-containing polysilicon in a fine shape by photolithography, and then covering the entire surface of the semiconductor substrate with an oxide insulating film. The emitter and the base contact hole are simultaneously formed in a cell layer by coating the semiconductor substrate with ions, implanting ions at high concentration into the surface of the base region through an oxide insulating film, and uniformly removing the oxide insulating film vertically to the semiconductor substrate. It is formed by lines.

As described above, according to the present invention, an extremely fine emitter shape is possible, and since the highly concentrated ion-implanted base extends to the very vicinity of the emitter, the base resistance can be significantly reduced and the noise characteristics at high frequencies can be improved. Furthermore, since the emitter and base contact holes can be obtained by self-line without using photolithography, there is no need to worry about misalignment due to alignment accuracy, and the yield in the manufacturing process is significantly improved, providing inexpensive products. It is possible.

Hereinafter, one embodiment of the present invention will be described in more detail with reference to the drawings. The embodiment will be explained using an NPN transistor as an example.

First, as shown in FIG. 2a), a P-type base layer 2 is formed on an N-type silicon substrate 1 by ion implantation, thermal diffusion, or the like. 3 is an oxide insulating film. Thereafter, a polysilicon layer 6 containing N-type impurities such as silicon is formed. Next, as shown in FIG. 2b), the impurity-containing polysilicon 6 is selectively etched away by leaving the photoresist 7 in a shape of about 1 to 2 .mu.m and using it as a mask using a normal photolithography technique. There are two methods for removing polysilicon: wet etching using a hydrofluoric acid-nitric acid mixture system and dry etching using a CC/4 gas. However, when performing submicron microfabrication, dry etching initially removes about 90 wafers. If it is removed and then finished by wet etching to finish the remaining and over etching, a finer pattern can be obtained with higher accuracy than the pattern obtained with the 7-photoresist. Next, as shown in Figure C), after removing the photoresist 7, the entire substrate is covered with an oxide insulating film 8. This oxide film 8 is 5
A CVD oxide film obtained by growing an oxide film through a chemical reaction at a low temperature of about 00°C to 600°C is
It is good to form around ^~5000i.

Next, as shown in Figure d), P-type impurities such as boron are ion-implanted at a high concentration through the oxide film 8 to form a low-resistance base region 9, and a cine dull material is formed by heat treatment at about 900°C to 100°C. Emitter region 1 (1
- Diffusion. Next, as shown in figure e), dry etching is performed in a direction perpendicular to the semiconductor substrate using a parallel plate active sputtering device or the like. By dry etching the oxide film 8 using, for example, C) IF system gas, it is possible to obtain a sufficient etching rate ratio of the oxide film and silicon, for example, 15:1, and to form a parallel plate. By using a mold active sputtering device, etc., etching is performed only in the vertical direction with almost no side etching, so that the side surfaces of the polysilicon and the top surface of the base-collector junction are etched by the process shown in d) above. The polysilicon layer 6 can be left with the same oxide film thickness.
The upper emitter hole 11 and the base contact hole 12 above the heavily doped base region 9 are simultaneously obtained by self-alignment. Finally, as shown in FIG.
41c is formed.

As described above, as shown in FIG. 2 f), the emitter layer 10 is formed of the polysilicon layer 6 and has an extremely fine shape of about 0.5 to 1.0 μm, and has a relatively high ratio between the emitter base contacts. The base area of the resistance is 0.2-0.3
Since the thickness is on the order of .mu.m and the rest is the heavily doped base region 9, it becomes a transistor with significantly reduced base resistance and has excellent low noise characteristics.

Furthermore, since the emitter hole 11 and the base contact hole 12 can be obtained simultaneously by self-line without using photolithography, there is no misalignment due to the precision of metal fitting, the process can be shortened, and the product can be provided at a high yield and at low cost. .

It goes without saying that the present invention can also be applied to PNP transistors.

[Brief explanation of the drawing]

1a) to 1C) are cross-sectional views at each step for explaining a conventional manufacturing method, and FIGS. 2a) to 2f) are sectional views at each step in a method for manufacturing a transistor according to an embodiment of the present invention. FIG. ]...Silicon substrate, 2...Base region, 3...Insulating film (oxide film), 4...
Emitter hole, 5...Base contact hole, 6.
...Emitter region, 7...°Photoresist, 8...Insulating film, 9...Base high concentration layer, 10...Emitter region, 11...
・Emitter contact hole, 12...Base contact hole, 13...Emitter electrode, 14...
...Base electrode. Figure 7 2nd area/θ 7 Figure 2

Claims (1)

[Claims] A process of forming a polycrystalline silicon layer on the entire surface of a base region formed on a semiconductor substrate, a process of selectively etching and removing the polycrystalline silicon layer using photolithography, and a process of forming an oxide insulating film on the entire surface of the semiconductor substrate. a step of ion-implanting impurities into the base region through the oxide insulating film to form a highly concentrated base region; and a step of uniformly removing the oxide insulating film in a direction perpendicular to the semiconductor substrate. A method for manufacturing a semiconductor device, comprising: