JPS6068659A - Field effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent the deterioration of element characteristics such as scattering, recombination of carrier in the boundary with different type semiconductor or between the semiconductor and an insulating film by forming a channel completely surrounding a P-N junction. CONSTITUTION:Electrons of carrier are flowed from a source side to a drain side, i.e., in a direction of an arrow in the drawing in a channel 7. A region that the electrons are flowed by potential barrier formed at the P-N junction is limited at this time. Accordingly, the channel region can be adjusted by altering the position of the potential barrier by the value of the voltage applied to electrodes 5. Since the channel corresponding to the passage of the electrons is completely limited to the interior of a semiconductor layer 13, the channel can be sufficiently isolated from a hetero junction presented in the boundary of semiconductor layers 12, 13. Further, the channel is formed sufficiently separate from the surface. As a result, the deterioration in the characteristics such as operating speed or mutual conductance caused by the scattering and recombination of the carrier in the hetero junction can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a field effect transistor having high operating speed and high amplification, and a method for manufacturing a gate portion thereof.

FIG. 1 shows a cross-sectional view of a gate portion 1 of a conventional device of this type. A p-type semiconductor layer 4 is provided within an n-type semiconductor layer 3 laminated on a semi-insulating substrate 2. In this device, the channel layer 7 for majority carriers (electrons) is of n-type, which corresponds to the p-type semiconductor 4. Substrate insulation layer 2
1 is formed in a region surrounded by the first surface insulating film 6. The operating principle of this device is to control the conductance of the channel in the direction perpendicular to the plane of the paper, which is obtained by making the size of the channel 7 variable. Therefore, if you change the voltage applied to the voltage @5 connected to the p-type semiconductor,
It is possible to control the number of carriers flowing inside the cell in a direction perpendicular to the plane of the paper. However, in this structure, since the lower part of the channel is formed at the interface of the semiconductor layer 2.3, there is a drawback that it is difficult to obtain high-speed operation due to the effects of scattering and the like when carriers move. Unfortunately, there was also a loss in mutual conductance due to interfacial recombination. This situation is also common in the upper part of the channel formed at the interface with the insulating film.

In order to overcome these drawbacks, the present invention provides a field effect transistor in which a cell completely surrounded by a PN junction is formed, and a method for manufacturing the same.

The present invention will be described in detail below with reference to the drawings.

FIG. 2 shows a cross-sectional view of the gate portion 11 according to an embodiment of the present invention. In a layered structure in which an n-type InGaAsP semiconductor layer 12 having a bandgap energy of 0.95 eV and an n-type InP semiconductor layer 13 are laminated on a semi-insulating InP substrate 2, a p-carving blunt is selectively introduced to form a p-type semiconductor. Region 4 (shaded area) is formed.

In terms of the layer structure, the PN junction 16 (indicated by a broken line) is formed within the semiconductor layer 13 and almost at the interface between the semiconductor layers 12 and 13, and when viewed in cross section as shown in FIG. It has a closed shape within the layer. Therefore, the channel 7 formed in the region surrounded by the PN junction exists completely only inside the semiconductor layer 13. An electrode 5 is connected to the p-type semiconductor layer 4, and an exposed portion of the PN junction surface is covered with an insulating film 6. moreover,
A drain electrode 15 is provided to be connected to semiconductor layers 12 and 13. Although not shown in FIG. 2, there is a north electrode connected to the semiconductor layers 12 and 13 at a position symmetrical to 15 with the gate electrode 5 in between.

The operating principle of this device is similar to that shown in FIG. 1, but electrons, which are carriers, flow in the channel 7 from the north side to the drain side, that is, in the direction shown by the arrow in the figure. At this time, it goes without saying that the region in which electrons can flow is limited by the potential barrier formed at the PN junction. Therefore, by changing the position of the potential barrier depending on the value of the voltage applied to the electrode 5, the channel region can be adjusted. In FIG. 2, the electrode 5
An example is shown in which a reverse bias is applied to narrow the channel by the area indicated by the horizontal line 14 compared to when no voltage is applied. In this way, the channel corresponding to the path of electrons can be completely limited to the inside of the semiconductor layer 13, so that the semiconductor layer 12
, 13, the channel can be sufficiently separated from the heterojunction present at the interface of .

In the embodiment of FIG. 2, it goes without saying that the channels are also formed at a sufficient distance from the surface. As a result, deterioration of characteristics such as operating speed mutual conductance caused by scattering and recombination of carriers in the heterojunction can be prevented.

Next, a manufacturing method for obtaining the structure shown in FIG. 2 will be described. FIG. 3 shows an InGaAsP layer 12 stacked on a semi-insulating InP substrate 2. This is a cross-sectional view when Be ions are selectively implanted into a multilayer semiconductor layer consisting of one InP layer and three upper layers. B in the area surrounded by broken line 9
In order to implant e-ions, the surface is covered with silicon nitride films 6, 8 and a resist 10 as masks.

Resist 1011Be is removed immediately after ion implantation. By the way, since the diffusion coefficient of Be in the InGaAs2 layer 12 has a larger value than that in the InP layer 1, the Be in the InGaAs2 layer 12 is Atoms spread laterally. Therefore, if the lateral size of the ion implantation mask 8 is set to less than about twice the spread of Be atoms due to thermal diffusion, the InGaAsP directly under the ion implantation mask 8 can be
Be-based acceptors are supplied to the layer 12 by diffusing from both sides, and both diffusion regions touch at the center, making the entire InGaAsP layer 12 directly under the mask 8 p-type.

On the other hand, within the InP layer 3, which has a small diffusion coefficient, thermal diffusion of Be atoms hardly occurs, so Be atoms after heat treatment
The atomic distribution is almost unchanged from that after implantation. Therefore, it is form 11 (7) it. Thereafter, the mask 8 is removed by a known process, and the electrode 5 shown in FIG. 2 is formed.

FIG. 4 shows another embodiment of the invention.

In this embodiment, two or more electron channels 7 are arranged side by side, and can be obtained by connecting the required number of the embodiments shown in FIG. 2 in the horizontal direction.

In the second embodiment below, the method of forming the channel with InP was described, but it is also possible to form it with 1nGaAs P II, which has a smaller bandgap energy. In this case, it goes without saying that the semiconductor layers sandwiching the semiconductor layer must have a large diffusion coefficient for Be atoms.

Finally, in addition to the above-mentioned Be, zinc, cadmium, etc. can also be used as the acceptor type impurity.

As explained above, the gate junction of the field effect transistor according to the present invention has a structure in which the channel through which majority carriers flow is completely surrounded by a potential barrier. Factors that degrade device characteristics, such as carrier scattering and recombination at the film interface, can be removed.

1. According to the manufacturing method of the gate part according to the present invention, 1L has a different thermal diffusion coefficient for acceptor type impurities.
In a semiconductor multilayer film structure in which l-V group compound semiconductors are alternately stacked and a semiconductor layer with a small diffusion coefficient is provided as an intermediate layer, acceptor-type impurities are selectively removed using ion implantation technology, followed by heat treatment. Since it consists only of steps, it not only simplifies the manufacturing process, but also
There are advantages such as improved yield and improved device reliability.

[Brief explanation of drawings]

FIG. 1 is a sectional view of the gate portion of a conventional field effect transistor, FIG. 2 is a sectional view of an embodiment of the device of the present invention, FIG. 3 is a manufacturing process diagram of the device of the present invention, and FIG. 4 is a diagram of the device of the present invention. This is another example. 1...Gate part of conventional field effect transistor, 2.
... semi-insulating semiconductor substrate, 3... n-type semiconductor layer, 4.
... N-type semiconductor layer, 5... Electrode, 6, 8... Insulating film, 7... Channel, 9... Acceptor type atom introduction region, 10... Resist, 11... Present invention 12.13...n-type semiconductor layer, 14...depletion layer region, 15...electrode, 16...
PN junction. Patent Applicant Japan 'Kameshinkiwa Public Corporation Representative Person Hakusui Tsune Yugai 1 Figure 1 Figure Fi2 Figure 3 Figure 0

Claims (2)

[Claims] (1) 11 having at least two or more heterojunctions
In a field effect transistor having a gate portion including a PN junction formed in a 1-V group compound semiconductor multilayer film,
The PN junction of the gate portion is formed across at least two heterojunctions, and the majority carrier channel is surrounded by PN junctions in the direction perpendicular to the direction in which the carriers flow. Characteristics of field effect transistors. (2) An n-type first 1t-v group compound semiconductor and an n-type second river-V group compound semiconductor having a larger diffusion coefficient in line with the acceptor type impurity are arranged in order from the surface side. , a step of forming a semiconductor multilayer film stacked to form a first semiconductor and a second semiconductor, and introducing acceptor-type impurities into each region divided into at least two parts of the semiconductor multilayer film by ion implantation. , a step of expanding the acceptor type impurity 1 into the divided region in the second semiconductor layer by applying a subsequent heat treatment, and the channel of the majority carriers is connected to the PN junction in the direction perpendicular to the direction in which the carriers flow. A method for manufacturing a field effect transistor, characterized in that it is formed so as to be surrounded.