JPS6068737A - Identifying and regenerating circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (al) Technical Field of BA Consideration 4 The present invention relates to improvement of a data reception width regeneration circuit in digital transmission.

(bl Technology background) With the launch and spread of data processing technology, data processing systems have gradually become faster and wider in area, and data input and output from terminal devices scattered over a wide area is transmitted via lines, etc. The data received via the transmission line is distorted by jitter caused by delay or noise due to transmission, and in order to improve the RAS, the received data is usually subjected to reproduction processing. is applied to return the data waveform to its original form.

This article concerns the reproducing circuit.

(C) & Next technology and problems Traditionally, second-second modulation methods have been proposed for digital data, and the most widely used method is NRZ, which modulates binary information with 1 in the forward direction and 0 in the reverse direction. Correspond to other NRZI
is a method that inverts the level only when it is 1 and maintains the previous level without inverting when it is 0, and the number of level inversions in the same bit time is 1/2 compared to simple RZ, and the allowable phase is The deviation is ±0.5 (±900) and other modulation methods FM
, PM, MFM, Kun.

Although it has a feature that can be made larger compared to M-NRZ etc., on the other hand, external synchronization No. 16, which is independent from No. 8, is required for the reproduction of Ringo.

A time chart of the NRZ data reproduction method in Karumai is shown.

Figure 1 shows a clock that is the same as the data pi HA return frequency.
FIG. 2 shows the data bit repetition frequency and a clock twice the same, and FIG. 3 shows the data bit repetition frequency and a clock three times the same. In NRZ and NRZI, there is a one-to-one correspondence between the bit repetition frequency wave and the maximum repetition frequency of level change of No. 48 [7] However, other modulations in which the maximum repetition frequency of level change is twice the bit repetition frequency For example, twice the bit repetition frequency in PM.

The relationship between the signal level change and the clock phase when clocks with frequencies 4 times and 6 times are made to correspond is the same as the relationship shown in FIGS. 1 to 3 above, except that the correspondence between the level change and the bit code is different. Even in the case of collapse as shown in Figures 1 to 3, if the periods are independent, there is an advantage that the transmitting and receiving timing circuits can be shared for each transmitting and receiving device, but it is difficult in practice, and it is difficult to use the digital signal on the receiving side depending on the received data. A pulse generation circuit for synchronization, such as a digital phase synchronization circuit (D
PLL) is used to control the sampling clock. For example, is there an advantage that the one-to-one → non-blink clock method shown in Figure 1 requires a low clock frequency? It is necessary to perform phase adjustment at the time of test #/adjustment, and there is the hassle of having to adjust the phase every time the corresponding received data differs. In the method using the one-to-two sampling clock candidates A and B shown in Figure 2, one clock is normal in the sampling clock candidate B in section 2-3, but the other clock malfunctions, resulting in an allowable phase shift of ten clocks as shown in Figure 1. The ratio is narrower to ±0.25 compared to 0.5, which is less advantageous than the 1:1 ratio shown in FIG. In the example of 1:3 sampling clock candidates C and D in FIG. 3, the allowable phase shift becomes even narrower, but when majority decision is made, the allowable phase shift of ±0.33 can be secured.

However, the disadvantage is that the frequency of the sampling clock becomes higher.

The purpose of "fdl generation Qlj%" is to obtain the optimal phase from among the sampling clocks and complementary central phases, which is twice the maximum repetition frequency of level change in the conventional system. By selecting the position and creating a sampling link circuit with every other 1:1 frequency, we can eliminate the advantage of the large allowable phase shift of the 1:1 sampling link circuit, and it is a field of adjustment. The present invention aims to provide a sharply discriminating reproducing circuit that reproduces the waveform of input data using a sampling link cropper that selects the optimum phase by automatic IQ selection so as to obtain an effect similar to a 1:3 majority decision.

(el) Structure of the Invention The object of the present invention is to provide means for generating a clock having a repetition frequency twice the maximum repetition frequency of level change in digital input data and a reverse phase clock thereof; A 10m2 phase identification stage for collating and identifying and holding the optimum phase for level detection; This is achieved by providing a digital input data identification and regeneration circuit comprising means for extracting and creating a sampling clock with an optimal phase, and the regeneration means identifies and reproduces level changes in the input data according to the output of the clock creation means. You can.

(fl Embodiment of the Invention An embodiment of the invention will be described below with reference to the drawings.

FIG. 4 is a time chart showing the concept of the identification reproducing circuit in one embodiment of the present invention, FIG. 5 is a block diagram of the identification reproducing circuit in one embodiment of the present invention, and FIG. 6 is an example of its implementation, especially phase identification. FIG. 7 is a time chart of the phase identification and clock creation circuit, and FIG. 8 is a time chart of the data reproducing circuit.

In the figure, 1 is a clock generation circuit, 2a is a first phase discrimination circuit, 2b is a second phase discrimination circuit, 3 is a beam lock generation circuit, 4 is a data reproduction circuit, 31 a, b41''/2 molecules tJrt2r+ FF, a, 2a , 3a, 1b, 2b,
3b is a flip-flop circuit for J-, LA-1 to 4 are latch circuits, AND Ia, 2a, 3a, 4a, Ib12
b, 3b, 4b#5a, 5b+6a, 6b+6C+6d
is AND circuit +0Ria.

2a, Ib, 2b, and 3 are OR circuits, and INV is an inverter. The clock generation circuit is twice the level change frequency of the input data, and since the input data here is NRZ, there is a one-to-one correspondence between one bit of input data and a level change, so one bit of input data corresponds to two clocks. Generate a normal phase clock (CK) of the frequency and a negative phase clock (*CK) delayed by iso', and send CK to the first phase identification circuit 2a, *CK to the second phase identification circuit 2b, and the clock generation circuit 3. Send to. 1st. Second phase identification circuit 2a
, b is a total of four sets aO~, bQ-, c(1~ and dO~
The optimum phase is identified from among them, and a signal is sent to the clock generation circuit 3 to identify one set, for example, bo~ in the example of FIG. 4, which corresponds to the optimum corresponding position to the input data. The clock generation circuit 3 is the first. According to the job-specific signals from the second phase identification circuits 2a and 2b, the bits of the input data are matched from among the four phase combinations, and a sampling clock having the optimum phase is obtained and sent to the data reproducing circuit 4. It receives input data, performs synchronous reproduction using the sampling clock, and sends it out as reproduced data. C from clock generation circuit 1
K, *CK is the h frequency divider 31a of the clock generation circuit 3,
7 in FIG. 7 as sampling pulse candidates CKA, *CKA, CKB, and *CKB, respectively.
-2aa-bb and applied to ANDba-d. On the other hand, the input data is the first one along with the data reproduction time jfi4. The signal is applied to the second phase discrimination circuits 2a and 2b, and compared with CK and *CK in a counter row consisting of FF1a to 3a and FF1b to 3b, respectively.

First of all. The second phase discrimination circuits 2a and 2b have the same circuit configuration, and CK is applied to FF1a to 3a, and FF1
The only difference is that *CK is applied to a to 3a. C
K and *CK are set to double the circumference for the bit repetition of the input data, and for the data original without transformation, for example, C1 (is synchronized with the 2 bits corresponding to the rising part). The input data is delayed by the transmission line or due to jitter, the timing of the waveform is shifted, and the input data is CKt or *C.
Three or two K correspond in undefined phase.

For example, 7-1 when the three digits of CK or *CK correspond.
As in example 1 of single person data, level 1 is detected at ``+cO, aO, AND2a obtains an AND signal, AND6b is selected by %A agate signal via LAla, and C
*CKA of 7-2ab corresponding to O~ is sent out as a sampling clock. al, cQ.

When the level is 0 at aO, the reverse logic is AND 1 from a via LAl and the A gate signal *CKA7%
Sent out. The same is true when using Nitta bO, d□, and J. Next, 2 CK; 7-1 when due to E or *CK
Shown in 2-7-12h. 7-12 person data When input as in example 2, CQ by CK and *CK.

Is there a match between a, dQ, and bl? -AN shown in 12c
The D4a output and the AND4b output shown by the dotted line 7-12f are obtained. In this case, since the AND4a output is in advance, the LA4 Q output is AND3a as the E day number 1.

4a and the output of AND4a is suppressed.
D4a to LA and AND5a are red and white and ANIJ6C of C gate is enabled and 7 2aaCKA is 7
-12h Sent as OR3 output. Another 7-1
On the other hand, in the three-person data example 3, the ANDJa side is suppressed and AN
7 by D gate ANL) bd by the output from D4b
-2baCKB is sent as the 7-13110R3 output. The sampling clock from OR3 is applied to the data reproducing circuit 4, which outputs the applied input data as a reproduced waveform as shown in FIG. 8-8-1a to 8-3C.

The above explanation has been made by ignoring the operation delay and signal propagation delay in FFs 1a to 3a, il) to 3b, but at high speeds where the operation is affected, the FFs of CK and *CK.
In the application between 1a and 3a and between 1b and 3b, a phase sleeve shall be applied by appropriate delay means etc. to operate.Also, the above is an example of NZR entrance data, but 1 data bit like PM is used. When has two levels, it can be realized in the same manner by considering replacing the bit-based t level change with reproducing the data waveform. In this case, since there is a two-level change for one bit, the CK+ per hit is
*4 clocks with 41 notes will be used as CK.

Since this embodiment is configured in this way, a sampling clock with a phase suitable for R is identified from among the four types for one bit of the input take, and thereafter, the identified timing is fixed and the data input is reproduced. An identification reproducing circuit that automatically performs the actual procedure is obtained.

fgl As explained in detail of the invention, a sampling clock whose optimum phase corresponds one-to-one to the input data is automatically extracted using a double frequency clock instead of using the triple frequency of the input data as in the conventional case. This is useful because it allows the person skilled in the art to provide an identification and reproducing circuit that can maintain a high allowable phase shift without having to be conscious of phase adjustment each time.

[Brief explanation of the drawing]

FIG. 4 is a time chart showing the concept of the identification reproducing circuit in an embodiment of the present invention; FIG. 5 is a block diagram of the identification reproducing circuit in an embodiment of the present invention; FIG. 6 FIG. 7 is a block diagram of a specific example of the phase identification and clock generation circuit, FIG. 7 is a time chart of the phase identification and clock generation circuit, and FIG. 8 is a time chart of the data reproducing circuit. 1.1, l is a clock generation circuit, 2a is a first phase discrimination circuit, 2b is a second phase discrimination circuit, 3 is a clock generation circuit, and 4 is a data regeneration circuit.畢 1 Pot tea 2 Mei 3 Old 20th No. 2F 1 Ku 4 (Japanese ν year 4E'I 5th Kumu 7th day・〃 7-rt Skadata IH 7-/2), Katei-kuri 2 1-/;! g LAIbQ person p 1-tzh oR3mj) 7-13 Hekachita now” 3 7-73cl+ND40-#-””--1111-7-
L3f AND4b Out cuff-L3h OR3 Kaka sitting 8 mouth

Claims (1)

[Claims] Means for generating a clock having a repetition frequency twice as high as the maximum repetition frequency of level change in digital input data, and a reverse phase clock thereof, and comparing the positive phase and negative phase clocks with the input data to determine the optimum phase for level detection. First, identify and retain. second phase identification means, first
．． The reproducing means extracts and creates a sampling clock of the optimum phase from the positive and negative phase clocks every 1/2 cycle according to the identification signal from the second phase identifying means, and the reproducing means generates the input data according to the output of the clock creating means. A digital input data identification/reproduction circuit characterized by identifying and reproducing level changes.