JPS6070880A - Defect compensating circuit of solid-state image pickup element - Google Patents

Abstract

PURPOSE:To constitute a defect compensating circuit with inexpensive memory elements by assigning a memory to store position information to each horizontal line and storing imaginary position information to a horizontal line where no defect exists. CONSTITUTION:An address of a memory 18 is connected to an output of the 1st counter 16 and a different address is given respectively to each horizontal line of a CCD solid-state image pickup element 11. The position information having a defect in a horizontal line corresponding to the image pickup element 11 is stored in an address given to each horizontal line. As to the horizontal line where no defective picture element exists, the address is stored in an imaginary horizontal direction is stored in the corresponding memory.

Description

[Detailed description of the invention] Technical fields> The present invention relates to a defect compensation circuit for a solid-state image sensor.

<Prior Art> In a solid-state imaging device using a CCD or the like, it is difficult to manufacture a defect-free device, and normal video signals may not be obtained locally due to crystal defects or the like. In order to deal with such inconveniences, attempts have been made to substantially increase the yield of solid-state imaging devices by electrically compensating for the defects, partially at the expense of resolution.

FIG. 1 is a block diagram showing a conventional solid-state imaging device in which defects associated with the solid-state imaging device are electrically compensated. In the figure, 1 is a solid-state image pickup device, 2 is a digital camera for amplifying the video signal from device 1, 3 is a defect compensation circuit, 4 is a vertical counter that counts horizontal scanning lines, and 5 is the water position of a pixel. 6 is a digital memory that stores position information of each pixel of the solid-state image sensor I, and 7 is a pulse generation circuit that supplies clock pulses to each of the above-mentioned circuits.

Here, the memory 6 stores one memory for each pixel of the solid-state image sensor 1.
Information indicating the presence or absence of a defect is stored at each address corresponding to pair 1, and the information at the address corresponding to each pixel is read out by the outputs of the vertical and horizontal counters 4 and 5, and this is supplied to the defect compensation circuit 3. The video signal output from the amplifier 2 is compensated. The video signals of neighboring pixels are used for compensation, and although the resolution is sacrificed to some extent, it is possible to obtain a video signal that compensates for defects, and even a solid-state image sensor with some defects can be effectively compared to a defect-free device. It can be used almost unchanged.

However, in this way, each pixel I/C 1 to 1 is stored in the memory lJ6.
If information on the presence or absence of defects is stored in correspondence with the above, there is a drawback that an enormous capacity (for example, approximately 200 bits in the case of 400 pixels horizontally and 500 vertically) is required for the memory 6.

On the other hand, a defect correction circuit has been proposed in which the memory capacity is reduced by storing only the positional information of the defective part in the memory without storing the positional information of the defective part.

However, although this method can reduce the memory capacity and width, it is not necessarily advantageous because it increases the number of matching circuits for comparing addresses and complicates peripheral circuits.

<Object of the Invention> The present invention was devised in view of the problems of the conventional solid-state image sensing device described above. It allocates a memory for storing position information for each horizontal line, and By storing fictitious position information, a defect correction circuit with an appropriate memory capacity and a simple peripheral circuit is provided.

<Embodiment> Fig. 2 shows an embodiment of the present invention, and is a block diagram of a defect correction circuit using CCI as a solid-state image sensor. A video signal 76 output from the solid-state image pickup device 11 that may include a plurality of points is amplified by the video amplifier 12 and then applied to the A terminal of the analog switch 13 .

The output of the video amplifier 12 is also once inputted to an analog delay element 14 whose delay time is set to, for example, one horizontal period, and after being delayed, the analog switch 12 is
is applied to the B terminal of The switch 13 switches either the Δ or B terminal to derive a video output. The solid-state image sensor 11 and the delay element 14 are driven by a clock signal φ output from a timing generation circuit 15, and the timing generation circuit I5 is driven by various pulse signals Fl, V, which will be described later.
Form D, HD, 1st FJ Unc 16. 2nd Kaunk 17. Controls the operation of memory 18 and matching circuit 19. That is, VD and HD outputted from the timing generation circuit 15 are vertical and horizontal synchronizing pulses, respectively, and Fl is a signal that distinguishes fields (for example, logic ""1 in odd fields).
This is a “logic 0” signal in an even field). The above F1 signal and Vl) signal are applied to the clear terminal of the first counter 16 via the AND gate 20, and the H'v
The signal is applied to a first counter 16 and a second counter 17. Therefore, the counter 16 counts 1 per frame.
The output of the counter 16 indicates position information (vertical address) indicating from which horizontal line the output is currently being output.

The number of stages of the first count 16 (ri, 10 bi when dealing with the old $C Rikijin video signal) (1024 wood minutes) is sufficient. On the other hand, it is cleared by the second count l7ip+1) signal, and if the next H[,) signal 1 is cleared, the CCD
Transfer port y φ ((Thus, the count is sequentially counted up. Therefore, the output of the second counter 17 is the positional information (water, The number of stages required for this second counter 17 is CC
Usually 9 vias (512 pixels) are sufficient, determined by the 1VN image resolution in the water direction of D.

Now, the address of the memory 18 is connected to the output of the first counter 16, and a different address is given to each horizontal line of the solid-state image element 11 to be accessed. In this way, the location information (horizontal address) where a defect exists in the corresponding horizontal line of the image sensor 11 is stored at the address obtained for each horizontal line (/(-Lj).The memory I8 is stored as described above. Since an address is set for each horizontal line, it is possible to deal with cases where there is no defect in the horizontal line or cases where there is a defect at one location.

However, in an actual CCD image pickup device, it is rare for a horizontal line to contain defects in two or more locations, and as in this embodiment, the memory 18 stores information about a maximum of one defect in each horizontal line in the horizontal direction of that pixel. If the position information of the device can be stored, defects can be compensated for and the device can be put to practical use.

The memory 18 sequentially reads the positional information of defects on each horizontal line in response to the address signal, and provides the information to the matching circuit 19. The other input terminal of the matching circuit I9 is
/φ gives the count value of the second counter 17 that sequentially counts the pixel positions in the horizontal line, and the memory 18
A comparison is made with the position information read from the matching circuit I9, and a control signal is given to the analog switch 13 with the output word DD of the matching circuit I9 active.

In this embodiment, only when No. 1 (DI) is active, the analog switch 13 is switched from the A side to the B full to switch to the video signal that has passed through the analog delay element 14 and output it. Here, the analog delay element 14 has a size of, for example, IH (in the case of a monochrome solid-state image sensor) 2
I) This is the CCD delay line (in the case of a color solid-state image sensor), and the video signal is replaced by the output signal from the surrounding pixels that have a high correlation with the defective pixel. For horizontal lines without defective pixels, write an imaginary horizontal address that does not exist in the corresponding memory. For example, if there are 400 pixels in the horizontal direction, 9 bits (φ ~ IFFH) Among the addresses, 1 to 190H are addresses corresponding to existing pixels, and l l" F l
Let l be a fictitious address. By selecting the above address, the output of the memory 18 and the output fd-i of the counter 17 will not be connected to each other in the horizontal line where there is no defect, and therefore the output of the matching circuit 19 will never become active. No defect compensation will be provided.

For example, the above embodiment shows a case where 9 bits are required as an output line from the memory 18, so it is configured using an EPROM having a capacity of 8 x 2 k bits or 8 x 4 k bits, which is easily available at present. In this case, multiple pieces of memory are required. Therefore, an embodiment that can be constructed using one 8-bit wide memory will be described with reference to FIG. In other words, using 2 bytes of memory, the horizontal address 1 of the defective pixel is
This is for storing individual parts, and the first part of the embodiment shown in FIG.
Instead of the counter 16 and the memory 18, three stages of monomulti circuits 21, 22, 23 . A circuit constructed using a counter 24, a memory 25, a launch 26, etc. is inserted, and the outputs of the memory 25 and latch 26 are inputted to one side of the matching circuit 19 in the same manner as in the previous embodiment. FIG. 4 is a time chart for explaining the operation of the circuit.

In Figures 3 and 4, the three-stage mono multi-circuit 2+
, 22 and 23 to form a signal HD2 having two pulse trains based on the HD signal.

This signal HD2 causes the counter 24 to
The count will be counted up twice. The contents of the memory 25 corresponding to the counter output changing by the first pulse of the signal HI)2 are held in the Djibouti 26. Therefore, the number of counter stages required is 11 bits, but the memory capacity is 8 bits.
x2" bits, that is, 8 Although a method has been shown in which the counter outputs are compared using a matching circuit, it is of course also possible to pre-centre the memory output to the counter and perform defect compensation using the output of the counter.

Effects> As described above, according to the present invention, memory is allocated for each horizontal line to store horizontal position information of defective pixels or non-existent imaginary position information for horizontal lines where no defects exist. By storing the following, it is possible to provide an economical defect compensation circuit for a solid-state image sensor, which can be constructed with only one easily available and inexpensive memory element and a simple peripheral circuit.

[Brief explanation of drawings]

Figure 1 does not show the defect compensation circuit of a conventional solid-state image sensor.
Figure 2 shows an embodiment 11 of the present invention: ccD.
Image sensor, 13. Analog switch, 14. Analog delay element, 15: Timing generation circuit, +6, l-
7. Counter, 18: Memory, I9. matching circuit.

Claims (1)

[Scope of Claims] 1) A solid-state image sensor formed by arranging a plurality of image sensors, and a memory for storing positional information indicating a defective location of the solid-state image sensor, and positional information read from the memory. In the defect compensation circuit that replaces the signal of a defective pixel of the solid-state image sensor with the signal of another pixel having a high correlation with the defective pixel based on A defect compensation circuit for a solid-state image sensor, comprising a memory that stores horizontal position information regarding a defective pixel included in the horizontal line at a set address. 2) Defect compensation for a solid-state image pickup device according to claim 1, wherein the horizontal position information of the defective pixel is set to information in which no corresponding position exists for a horizontal line without a defect. circuit.