JPS607208A - Phase shift synergetic fm demodulator - Google Patents

Abstract

PURPOSE:To improve the demodulation efficiency by keeping a phase difference of 90 deg. at the center frequency between two FM intermediate frequency signals inputted to a multiplier to balance output voltages and the demodulating operation. CONSTITUTION:An FM intermediate frequency signal applied to an input terminal IN is branched into two paths P1, P2 and an FM signal via the P1 is applied to the multiplier 3 by a limiter amplifier 5 as the 1st input signal S1. After the FM signal via the P2 is phase-shifted by phi by a phase shifter 2, the result is applied to the multiplier 3 by a limiter amplifier 6 as the 2nd input signal S2. A part of an output signal S0 demodulated by the multiplier 3 is applied to an integration circuit 8, which detects the amount of phase shift phi and adjusts the amount of phase shift of the phase shifter 2 so that the value is converged to a prescribed value when the amount is shifted from the prescribed value. Since the phase shifter 2 is set to phase shift the FM signal by phi(=90 deg.) at the center frequency f0 of the inputted FM intermediate frequency signal, the integration circuit 8 detects the amount of shift from 90 deg. and operates that the amount is converged into 90 deg. at all times.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a phase-shift synergistic FM in which a multiplier operates at an accurate operating point even when a rectangular wave signal is input.
This relates to a demodulation circuit.

Phase shift synergistic FM as one demodulation circuit in FM receiver
Demodulation circuits are known. Figure 1 shows the conventional phase-shift synergistic F
The configuration of the M demodulation circuit is shown in a block diagram. IN is an input terminal, U (J T is an output terminal, ■ is a big amplifier, 2 is a phase shifter, 3 is a multiplier, 4 is a low-pass filter, P1vP
2 is a signal path, S]lS2 and So are input and output signals to the multiplier.

In the above configuration, the FM intermediate frequency signal frequency-converted by the mixer of the receiver (ig machine) is applied to the input terminal IN, amplified and limited by the limiter amplifier l, and then branched into two paths PJeP2, and the path e1 The signal component S1 that has passed through the path e2 is directly input to the multiplier 3.
The signal component that has passed through is input into the multiplier 3 after being made into the 4H signal component S2 with a slight phase shift by the shifter 414.

Next, the multiplier 3 demodulates the FM signal wave by switching the above-mentioned signal component S] with the signal component S2 whose phase is shifted relative to it and taking the product of both signal components. Only the frequency im signal component is passed through to obtain the FM demodulated signal from the terminal 0 [JT.

In the FM receiver, the phase shifter 2 is tuned to the center frequency f of the FM intermediate frequency signal, and the signal component S
2 is configured to delay the phase of signal component S1 by 90'', and at this time, the average value of the cutting edge of the multiplier due to switching is 0.The second (2) is such an operation. (Cb for signal component s1 of aJ) (') Signal component S2 is J
If the phase shift relationship of '(t1~tz) = 90'' is maintained, the output of the switching signal 82 (7) The output of the FM human input signal S1 in the positive direction is (1(t2~ta) to the positive component like CJ) and negative component A2 (t3 to t4
) and #t) are equal, so the average value is 0. Therefore, by using the relationship obtained by shifting the phase of S2 by 99' with respect to S and K as a reference, and operating the multiplier 3 using this point as the operating point, the frequency of the f''M signal S1 is adjusted to the central station IS: Depending on whether the number fQK is high or low, the relationship between Sl and 82 is 9o0 and 90', respectively, as shown in Figure 3 (8), so the average value of the output signal So of CJ is Since they are negative and positive respectively, F
M codes can be demodulated.

Here, the specific circuit configuration of the phase shifter 2 in FIG.
As shown in the figure, ln is an input terminal, out is an output terminal, R is a resistor, C is a capacitor, and 8 is an amplifier.

This phase shifter 2 works as an all-pass filter and the input/output 4
The noise width ratio for No. B is l, and it operates so as to change only the phase.

This phase shifter 2 works to shift the phase of the signal component applied to the input terminal in via the path P2 by 〆=2tan ωRC, and by setting ω=l/RC, =90'(π/2)VCJ can be obtained, and the frequency f-phase 09 characteristic as shown in FIG. 5 can be obtained. Multiplier 3 at the same time
0 frequency f-i width (output voltage)% is also obtained, and as mentioned above, depending on whether the number of FM input signal stations is equal to the center frequency foK or high (or low) The output voltage of the multiplier 3 can be changed.

By the way, for such a phase shifter 2, a limiter amplifier l
The rectangular wave that has passed through (when M is added, this rectangular wave is composed of the fundamental wave and its madder harmonic components so that it is expanded into a Fourier-class peak (・, so 0=9♂ Even if you try to set it to The relationship of $=2tan ωIIC holds true ℃
・.

Figure 6 shows the signal waveform in such an operation, where the signal component SJ (limiter amplifier
signal component 82' which is the output of phase shifter 2 of bl for
is a waveform obtained by integrating Sl, and its rise time is determined by the time constants of the resistor R and capacitor C. Also, at this time, it is necessary to hold a voltage higher than the threshold voltage Vt for the multiplier 3 (to function as a switching signal), and this condition is satisfied after a delay of θ.
The signal S2 between 6 and 17 is added as an input to the multiplier p (like CJ) and the multiplier 30. Therefore, in the multiplier 3, the signal Sl of ta is switched with the signal S2 of (C) ld)
A signal So like this is output. Here, the average value of the signal So is not O but positive, so the unbalanced ff
Voltage voltage.

The fact that the relationship p = 9o' is not maintained even when ω-1/RCK is set in this way is because the center station wave number fo at which the blade becomes 0 in the more f-V characteristic shown in Fig. 7 deviates to f]. The original desirable characteristics (8J) become undesirable characteristics (IJJK).

The resistance date and capacitor C of the above timed zero circuit are HI7,
Even if you try to set a 90° relationship by controlling the rise time by adjusting the resistance R and capacitor C
Since there are variations in K, the realization is fin, and it is not possible to balance the cutting voltage.

Therefore, the multiplier 3 cannot operate at the II:411ii operating point, and the demodulation operation becomes unbalanced, resulting in a decrease in demodulation efficiency and an increase in distortion.

The present invention does not address the above problems.
A first limiter in which the intermediate frequency signal is input and the output is multiplied by p, a phase shifter which receives the above-mentioned FM intermediate frequency signal as input, and the output of this phase shifter as input. The object of the present invention is to provide a phase-shifting synergistic FMI tuning W5 that is configured to include a second limiter whose output can be used as the second power of the multiplier, thereby eliminating the conventional drawbacks. . Embodiments of the present invention will be described below with reference to the drawings.

FIG. 8 is a block □□□ showing a phase-shifting synergistic FM demodulation circuit according to an embodiment of the present invention. The same parts as in FIG. , 7 is an eye movement phase control (APC) circuit, which is composed of, for example, an integrating circuit 112i8.

The FM intermediate frequency signal applied to the input terminal IN is connected to two channels 12iP1. Pz and input to the first limiter amplifier 5 and phase shifter 2, respectively. FM via passage P1
The signal is amplified and limited by a first limiter amplifier 5 and then applied to a multiplier 3 as a first input signal S]. On the other hand! 2S P2 %: The passed FM signal is phase-shifted by the phase shifter 2, and then amplified and limited by the second limiter amplifier 6, and is outputted as the manual signal S2 of the 1st multiplier 3Km2. The reason why it is provided at the front stage of the pick amplifier 6 is to ensure that the input F~1 intermediate frequency multiplied signal wave is phase-shifted by DA in the sine wave state before being converted into the FM signal. After the signal is phase-shifted, it is converted into a rectangular wave and is applied to the multiplier 3 as a second human input signal.

A part of the output IB signal So demodulated by the multiplier 3 is applied to an integrating circuit 8, and this integrating circuit 8 detects the phase shift amount, and if the phase shift is deviated from a predetermined value, it is set to a predetermined value. It operates to adjust the phase shift amount of the phase shifter 2 so that it falls within the range of .

1, that is, the center frequency fi of the input FM intermediate frequency signal
fo K °C, phase shifter 2 moves the above FM @ number to X-90°
Since it is set to shift the phase by (π/2), the integration circuit 8 detects the amount of deviation from 90'' and works to always keep it within 90°.

FIG. 9 shows an equivalent circuit of the multiplier 30. 82
are differential amplifiers, each with a transistor Ql.

Q2 and Q3. Consists of Q4, ■ is a constant current source, 1
0w! e is the output current, 1(] is the resistance, and C1 is the capacitor. Vl and V2 are the voltages of the signal "1+82", respectively, and when vl is input to the differential amplifier 2, both K V
2 is a differential amplifier ^IK manually powered. vO is the output 8
The output current i6 of the differential amplifier A2 is expressed as follows.

Here, ie also serves as a constant current source for pruning the differential amplifier, and the output current 1 of Ruri is expressed as follows.

;” (1+v2/2H'r/Q) =↓(1+vI/211T/q + V2/2111'
/q +v1°v2/ (2RT/q)2) -(2J
As is clear from equation (2), when there is no input FM signal (only the center frequency fO is input), the above V1sV2 becomes 0 and 1o=1/4, so the multiplier 3
The output voltage Vo becomes a bias value expressed by Vo=(Voo-11·I/4).

When the signal FMi@ which has been set and modulated as VI+V2 is manually input, the output voltage Vo changes up and down with the candy as the center in accordance with the deviation of V1+V2 from the center station ehfo.

Again, Vl: VS! nωot v2 = v'sin (ω□t +yf(”) J2
If 0-'/q = a, ■o is expressed as follows.

This is processed by a low-pass filter and becomes J unwrapping 1.

1, that is, in equation (4) above, Da(ω)=90°(π/
2) When K is set (phase difference of π/2 at center frequency f), it becomes lo-π/4, and the multiplier 3 becomes Vo more than described above.
Outputs an output voltage of = (Vcc R-π/4).

Figure 10 shows the multiplier 30 frequency if-output voltage V characteristic, where the manually inputted frequency signal for I''M medium r is at the center station e.
Characteristics when a ufo maintains a phase difference of π/2 (A
) and the characteristic (B) when the phase difference deviates from 2π by Δ〆. In characteristic (8), the accurate operating point is maintained, so the output voltage V is equal to the Vo
A desirable demodulation operation is performed by outputting (ief') of = (Vcc R''/4), and the demodulation distortion is minimized.

In characteristic (B), the center frequency f is shifted by Δf and fI
Since the FC transition occurs, the output voltage ν is ΔV from the above
Since the V6 ttc is shifted, the correct operating point cannot be maintained and the desired demodulation operation cannot be performed.

Therefore, demodulation distortion increases.

In this way, the phase difference of π/2 is not maintained.
Variations occur due to K temperature changes, changes over time, etc., resulting in ω-+
/'Re(ω-2πfo) is shifted, the local oscillation frequency of the mixer of the receiver fluctuates, and the center frequency ?fo shifts by Δf.

In the present invention, the FM intermediate frequency signal is
When the wave number fo deviates from the phase difference of π/2, the amount of deviation is detected by the automatic phase control circuit 7.

FIG. 11 shows a concrete circuit of the integrator circuit 8 constituting the automatic phase control circuit 7. It is composed of a low-pass filter r (therefore, a resistor 02 and a capacitor pc2, and has a sufficiently long time constant. When the output voltage of the voltage converter 3 is inputted from the terminal in, this integration circuit 8 generates an undesirable output voltage V which is shifted by ΔV from the desired output voltage vo.
The desired control voltage V responds only when O is input. is applied to the phase shifter 2 from the terminal out. As a result, the phase shifter 2 always works to maintain the phase difference of π/2 by adjusting the phase shift amount χ1.

12 and 13 show the method of controlling the phase shifter 2 using the integrating circuit 8. In FIG. By applying a control voltage vc from a circuit 8, the tuning frequency of the phase shifter 2 is varied. Fig. 13 is composed of a variable resistance element with zero resistance, and by applying the control voltage vc to this variable resistance element, the open leg of the phase shifter 2 is set. This allows I to be made variable.

The above variable capacitance elements are used for various reactance circuits (
・FET can also be used as a variable resistance element.
The channel resistance based on the gate-source voltage change can be used.

1jKlJ diagram shows the frequency 1!1lf-phase shift characteristic when the phase shift amount of the phase shifter is controlled by the automatic phase control circuit as described above. In the phase shifter 2, the center frequency f
, holds a phase difference of π/2, then Δf[J
If fI K is shifted by shifting ii, the phase g will also shift from π/2 (90') by π/2+Δg, so characteristic (8) changes to 4'# property (B). Change. As a result, the multiplier 3, which had been operating at an accurate operating point corresponding to the phase difference of π/2, changes its operating point (output voltage V) from the position of VO to vJ as shown in FIG.
The integration circuit 8 detects this change and adjusts the control voltage V accordingly. is added to the variable capacitance element or variable resistance element. As a result, each capacitance or resistance value returns to the phase shift amount tπ/2 and is varied in one direction based on the above-mentioned operating principle, so that the phase shifter 2 always maintains a phase difference of π/2 at the center frequency fO. Operate. This allows the multiplier 3 to operate at the correct operating point again, so that the characteristic CBJ is returned to the desired characteristic (pano).

As is clear from the above description, according to the present invention.

A first limiter that receives the FM intermediate frequency signal as an input and outputs the output signal p, a phase shifter that receives the FM intermediate frequency signal as the input, and outputs the output signal as the output signal of the phase shifter. and a second limiter that provides the second output of the multiplier, the center frequency (
・A phase difference of 90° is maintained -jF! :The output voltage can be balanced.

Therefore, the multiplier can operate at a precise operating point, and the harmonic operation is balanced, the harmonic effect is improved, and the occurrence of distortion can be reduced.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing conventional example 7, Fig. 2 (a) to (C)
J, Fig. 3 (heba aJ ~ (cJ, Q”p 3 (B
Figures a) to (C) and Figures 6 (a) to id) are waveform diagrams showing the conventional example, and Figures 4, 5, and 7 are circuit diagrams and characteristic diagrams showing the conventional example. , FIG. 8 is a block diagram showing the embodiment of the present invention, FIG. 1O and the 14th factor are characteristic diagrams showing the seventh embodiment of the present invention, and FIGS. FIG. 7 is a circuit diagram showing a seventh embodiment of the invention. 2... Phase shifter, 3... Multiplier, 5, 6... Limiter amplifier, 7... Automatic phase side J circuit, 8... Integrating circuit. Patent applicant Clarion Co., Ltd.≠4Zugaku6Figure6t7Rai8N

Claims (1)

[Claims] 1.1”M intermediate frequency signal is input and the output is the first of the multipliers.
A first limiter provided as an input, a phase shifter that receives the FM intermediate frequency signal as input, and a second limiter that uses the output of the phase shifter as a human power and provides the output as a second human power of the multiplier. A phase-shift synergistic FM demodulation circuit characterized by: 2. An automatic phase control circuit that receives the output of the multiplier as an input is provided in the phase shifter, and the phase shift amount of the phase shifter is automatically adjusted by this automatic phase control circuit. Phase-shift synergistic FM according to claim 1 characterized in
Demodulation circuit.