JPS6072232A - Pattern aligning method - Google Patents

Abstract

PURPOSE:To miniaturize the pellet of a semiconductor device by a method wherein, in the aligning method using a reducing projection exposure device, the inside of the scribe line of a semiconductor wafer mounted on a glass substrate is provided with a reticle mark to a photo mask that covers the wafer, and the outside is provided with a bright section pattern, and these marks are brought into alignment at the time of step and repeat. CONSTITUTION:The semiconductor wafer is mounted on the glass substrate 1, and, when it is covered with the photomask called a reticle, the reticle mark 5 provided to the photo mask is formed inside the scribe line 3 provided to the wafer. The bright section pattern 6 is provided in the dark region 4 outside the element region positioned outside the line 3, and the pattern 6 and the mark 5 are brought into pattern alignment by baking onto the wafer at the time of step and repeat. The number of marks is reduced in such a manner, and the miniaturization of wafers is then enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a pattern alignment method, and more particularly to a pattern alignment method when manufacturing a semiconductor device using a reduction projection exposure apparatus.

[Prior art]

The degree of integration of semiconductor devices is increasing year by year, and patterns are becoming increasingly finer. Accordingly, there has been a change in semiconductor device manufacturing equipment, and optical phosphorography technology has shifted from a contact exposure method to a reflection projection exposure method and then to a reduction projection exposure method.

Each of the above-mentioned lightless methods commonly transfers a bright and dark pattern formed on a photomask onto a wafer, and the photomask used in the reduction projection exposure method is called a reticle.

In the reduction projection exposure apparatus, the pattern drawn in the reticle is reduced to 175 or 1710, etc., and the pattern is formed on the entire surface of the wafer by step-and-repeat on the wafer.

Pattern alignment methods for reduction projection exposure equipment include a global alignment method, which aligns at least two locations on the wafer and then transfers the pattern by step-and-repeat scanning across the entire wafer, and a die-performer, which aligns each reticle pattern. There is an automatic alignment method.

The latter die-by-die alignment method can correct the position even if the wafer is deformed during the process, so it can provide a high degree of alignment accuracy.It also allows for mixed use with different non-light methods.

Generally, in the manufacture of semiconductor devices, elements are formed by overlapping patterns of several to more than ten layers. When layering this butter, alignment marks are used to ensure correct layering. Alignment marks are provided on both the wafer and the reticle.

The marks placed on wafers are called wafer marks.
The marks provided on the reticle are called readicle marks. If die-by-die alignment is to be performed on all the layers of the above-mentioned several to ten-odd layers of patterns, wafer marks for alignment must be formed in advance on the wafer for the number of times of overlapping. When positioning is performed using a redicle mark, the redicle mark is also transferred onto the wafer and cannot be used as a wafer mark in subsequent steps, so it is necessary to form the wafer mark at a different position. follow τ
However, the insertion area of the alignment mark into the reticle increases, resulting in an increase in the pellet size of the semiconductor device.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a pattern alignment method that eliminates the above drawbacks, enables alignment with a minimum number of wafer marks and reticle marks, and achieves miniaturization of semiconductor devices.

[Structure of the invention]

In the pattern alignment method of the present invention, in a pattern alignment method using a reduction projection m-light device, for a wafer 1 having a die-by-die alignment wafer mark in an element pattern area, a pattern alignment method that corresponds to the wafer mark on a reticle is provided. When the reticle mark for die-by-die alignment is placed at the position where the reticle mark is aligned with the wave mark, the next step is to place the reticle mark at the position of the wave mark where the reticle mark overlaps, and in an area outside the area of the element pattern. It is constructed by arranging a bright turn on the wavy mark, aligning the waving mark and the reticle mark, and performing step exposure so that the reticle mark is not transferred onto the waving mark.

[Explanation of Examples]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of a reticle used in an embodiment of the present invention.

In FIG. 1, a redicle mark 5 is arranged on a glass plate 1 in a part of an element forming region 2 that includes one bullet forming a semiconductor device. 3 is a scribe line, distances a and b between the centers of scribe line 3
indicates the size of one pellet, and steps a and b perform step-and-repeat in the X direction and the X direction. The area 4 outside the scribe line is a dark area, and a bright area pattern 6 for protecting wafer marks is arranged in a part of this area.

The bright pattern 6 is placed at a heated position a distance b from the reticle mark 5 in the X direction. Therefore, when step-and-repeat is performed, the bright pattern 6 on the way IS
and reticle mark 5 will be burned in an overlapping manner.

By making the bright pattern so large that it completely covers the wave mark and the reticle mark, it is possible to prevent the reticle mark from being transferred onto the wave mark.

FIG. 2 is another configuration diagram of a reticle used in one embodiment of the present invention. In FIG. 2, °C indicates a case in which four pellets are arranged in a reticle, which is different from the case in which one pellet 'f' is arranged in a reticle in FIG. In the figure, 2' is the element area of one pellet, and in this case, the dimensions a' and b' for two pellets are the step amount. Therefore, the bright part turn 6' is the reticle mark 5'.
The same effect as shown in FIG. 1 can be obtained by arranging it at a distance b' in the y direction from .

Therefore, the present invention can be applied without being limited to the number of pellets configured within the reticle.

Note that in the present invention, the reticle mark is transferred only to the first exposed wafer mark, but not to other wafer marks, so the next reticle can be aligned with the wafer mark that has not been transferred, and the reticle mark is transferred to the first exposed wafer mark. The wave mark can also be made into a pattern that is not transferred by overlaying it with a bright pattern and flashing it before development.

Conventionally, only the 1/takele mark was formed on the reticle, but since the reticle pattern is transferred to the same position on all pellets formed on the wafer, there are as many wafer marks and reticle marks for alignment as there are reticles. It becomes necessary to form l
It was necessary to increase the area of the pellet, but in the present invention, in addition to the reticle mark, a bright pattern is placed outside the area of the element pattern on the reticle at a position that overlaps with the wafer mark when step exposure is performed. The reticle is configured so that the mark is not transferred onto the wafer, and the wafer mark can be used for subsequent alignment, so only 91 72-ment marks are required per pellet or reticle, making it possible to reduce the pellet size. can.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to align a large number of reticle patterns with the minimum number of wafer marks and readicle marks, and as a result, it is possible to achieve pelletization of semiconductor devices. The effect is great.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a reticle used in one embodiment of the present invention, and FIG. 2 is a block diagram of another reticle used in one embodiment of the present invention. 1...Glass plate, 2.2'...Element area, 3...Scripe line, 4...Dark area outside the element area, 5゜51 ...Reticle mark, 6.6'...Bright pattern, a, a
"""' x direction step amount, b, b'...
・Y direction step amount. Camellia 2

Claims (1)

[Claims] In a pattern alignment method using a reduction projection exposure apparatus, for a wafer having a wafer mark for die-by-die alignment in an element pattern area, a readicle mark for die-by-die alignment is placed on a reticle at a position corresponding to the wafer mark. When the reticle mark is aligned with the wafer mark, the next step is to arrange a bright pattern at the position of the wafer mark where the reticle mark overlaps and in an area outside the area of the element pattern, and align the wafer mark with the wafer mark. A pattern alignment method characterized in that the reticle mark is aligned and step exposure is performed to prevent the reticle mark from being transferred onto the wafer mark.