JPS6072454A - Synchronism demodulator of digital frequency modulation signal - Google Patents

Abstract

PURPOSE:To improve the demodulating characteristic by using a signal after identification and regeneration to eliminate an unnecessary component in an error signal supplied to a voltage controlled oscillator thereby obtaining a reference carrier wave with less phase jitter. CONSTITUTION:Circuits 14-18 in chain lines are provided newly in addition. When a phase error thetae of signals eI, eQ to be inputted to identifiers 10, 11 is zero, the waveform of inputs vI, vQ, eI, eQ of each identifier and outputs eI, eQ is shown in solid lines in the figure, and the information a-f of an eye pattern of the detected outputs eI, eQ is delayed by a time T from information patterns a'-f' of the identifier outputs. The eye pattern of the signals eI, eQ with phase error thetae 0 is shown in broken lines in the figure. When ¦thetae¦<pi/2, however, the effect of the error thetae is eliminated completely from the identifier output. A signal Ve is obtained by the circuits 14-16 based on the identifier outputs eI, eQ, a 1/2 frequency division signal Vc and an error signal Ve. Although the signal vI includes a DC component having phase error information unnecessary AC component, the AC component when thetae 0 is nearly reduced to zero. That is, the phase jitter of the regenerated reference carrier wave is reduced when the carrier wave synchronism is established.

Description

[Detailed description of the invention]

[Technical field to which the invention pertains] The present invention relates to a demodulating device for a phase continuous digital frequency modulation signal. In particular, phase continuous digital frequency modulation schemes with a modulation index of approximately 0.5, e.g. MS K (Min
imun+ 5hift Keing), GMS
K (Gaussian filtrcd MSK)
The present invention relates to a method for synchronous demodulation of modulated waves generated by a method such as ``I'' FM (Tamed FM). [Description of Prior Art] Phase continuous digital frequency modulation signals are
Unlike the SK signal, the envelope of the modulated wave is constant, and the main spectrum is not affected by suppression due to output amplifier saturation, etc., so it is an advantageous modulation method for transmission lines including these nonlinear systems. In particular, phase continuous digital frequency modulated signals (MSK, GMSK,
TFM, etc.) is attracting attention as a modulation method that has a narrow occupied bandwidth and can perform more efficient demodulation using synchronous detection. In order to synchronously demodulate this signal, it is necessary to generate a reference carrier wave 11f from the received signal as a reference signal. Various methods have been proposed in the past for this purpose, but especially if it is intended to be used in the field of mobile communications, it is desired that the configuration be simple and that it can be easily fabricated into a monolithic IC. In this respect, the method using a modified Costa anti-loop (Japanese Patent Application No. 145371/1982) is superior. However, this method has a problem in that the phase jitter of the reproduced reference carrier wave becomes slightly large, causing deterioration in demodulation characteristics. This point will be explained below using demodulation of an MSK signal as an example. FIG. 1 shows the configuration of a conventional MSK synchronous demodulator using a modified Costas loop. In the figure, 1 is a received signal input terminal, 2 is a voltage controlled oscillator ('VCO), 3.4 is a phase comparator, 5.8 is a multiplier, 6 is a timing information input terminal, 7 is a timing clock regeneration circuit, and 9 is a loop. filter, 1
0.11 is a discriminator, 12 is a data reproducing circuit, and 13 is a demodulator output terminal. The operation when an MSK signal is input to the input terminal l in this configuration will be described below. When the bit rate and transmission angular frequency of the transmitted information series is ωC, the MSK signal eiM is expressed by the following equation. However, the positive and negative signs correspond to '' in the case of mark signal and space signal transmission, respectively. The in-phase reference carrier ep. has a phase error θe with respect to the carrier component of this signal. It is assumed that the voltage controlled oscillator 2 outputs the voltage controlled oscillator 2 and the orthogonal reference carrier wave elIQ. That is, eRl = COS
(ωct-1-θe) '-'-(21eRQ=-
sin (ωC

[+θe) ・−− −−− (31
Teal. These two reference carrier waves "R1% e RQ
The signals are input to phase comparators 3 and 4, respectively, and are compared in phase with the MSK signal eiM. As a result, the in-phase detection output els and the quadrature detection output eQ are obtained as the outputs of the phase comparators 3 and 4, respectively. If the phase comparator has a cosine phase comparison characteristic, el and eQ become as follows. Next, the detection signal
. . . is manually input to the i multiplier 5 and multiplied by each other, and the multiplier 5
If the output is e(.), multiplier No. 11 is obtained by multiplying by 2, . Based on this timing information, the clock reproducing circuit 7 reproduces the timing clock and its half-frequency wave VI % vQ % VC.Here, Vl = sin (π(->) - ------17)
v(,=-sin (π(-)) ---481V
C=CO5(π(−−))−−−−−−+91. The other three signals 1 and VQ are applied to the discriminators IO and II, respectively, and the clock signal v(, is applied to the multiplier 8. As a result, the error signal Ve IMed to the output of the multiplier 8 is ve = vP ′ v(; ----------tlol In the above, the first term is a DC component with phase error information, and the second term is a component caused by modulation. Among these, the first term A phase-locked loop is constructed by adding the DC component of to the voltage-controlled oscillator 2 via the loop filter 9, and the phase error θe quickly approaches zero, establishing the IM transmission interval. On the other hand, Equation 00) The AC component in the second term of is an unnecessary component,
This component is attenuated to some extent by the loop filter 9 and added to the voltage controlled oscillator 2&, but this component is added to the reference IH transmission wave eR1.
This increases the phase jitter of seBq, causing deterioration in demodulation characteristics. In order to prevent such deterioration, the band of the loop filter 9 can be narrowed to attenuate the alternating current component. Therefore, the limit for narrowing the band of the loop filter is 1.
＋）ru. Therefore, a certain degree of deterioration of the demodulation characteristics was avoided (1). [Objective of the Invention] The present invention solves the above-mentioned drawbacks, and aims to identify unnecessary components in the error signal applied to the th voltage controlled oscillator. It is an object of the present invention to improve the demodulation characteristics by removing the signal using the reproduced signal and thereby obtaining a reference general transmission wave with less phase jitter. Two phase comparators compare the phases of the signal and the regenerated carrier wave, which have a phase difference of 90 degrees from each other, to obtain two phase detection outputs whose phases differ from each other by 90 degrees.Based on these two phase detection outputs, In addition to obtaining a demodulated output, the product signal of these two phase detection outputs is multiplied by the frequency-divided 2 and 7 signals of the timing clock signal of the received signal, and this signal is delayed by a predetermined time. Obtain a signal. On the other hand, multiply the two mutually orthogonal signals obtained by discriminating and reproducing the above two phase detection outputs and the inverted signal of the above frequency-divided clock signal, and delay this signal by 1. A signal representing the difference between the two signals is obtained.The DC component of this difference signal is supplied as a phase control signal to the circuit that generates the carrier wave, and the carrier wave is synchronously controlled so as to follow the received input signal. .Explanation based on Embodiment C] FIG. 2 is a block diagram of a device according to an embodiment of the present invention.This circuit has a second circuit structure compared to the conventional circuit explained in FIG.
The feature is that the part surrounded by a dashed line in the figure is a newly added configuration. That is, the received signal at the received signal input terminal 1 is compared with the carrier wave of this received signal regenerated by the voltage controlled oscillator 2 by two phase comparators 3 and 4. The carrier waves given to these two phase comparators 3 and 4 are general transmission waves whose phases are different from each other by 90 degrees, and the outputs of these two phase comparators 3 and 4 have two phase detection signals orthogonal to each other. get the output. These two phase detection outputs are input to the first multiplier 5 and multiplied. On the other hand, the timing information of this received signal is input to the timing information input terminal r6, and the clock signal is regenerated by the clock regeneration circuit 7. One output vc of this clock regeneration circuit 7 has
A clock signal obtained by dividing the clock signal period of the received signal by two is sent out, and its output signal is given to one input of the second multiplier 8. The output of the first multiplier 5 is applied to the other input of the second multiplier 8. On the other hand, the two mutually orthogonal phase detection outputs obtained from the outputs of the two phase comparators 3 and 4 are input to two discriminators 10i and 11, which are respectively supplied with the recovered clock signal from the clock recovery circuit 7. Each digital signal is identified, the data is demodulated by the data reproducing circuit 12, and the demodulated data output is sent to the terminal 13. Here, in the circuit of the present invention, a third multiplier 14 is provided which branches the output signals of these two discriminators 10 and 11 into two inputs, and furthermore, the output of this multiplier 14 is used as one input. A fourth multiplier 16 is provided, and the other manual power of this fourth multiplier 16 is given to the second multiplier 8.
A signal obtained by inverting the frequency-divided clock signal by an inverting circuit 15 is input manually. Furthermore, the output of the second multiplier 8 is connected to a delay circuit 17 which provides a predetermined delay, and the delay circuit 1
7 and the output of the fourth multiplier 16 are led to two inputs of one subtraction circuit 18. The output of this subtraction circuit 18 is passed through a loop filter 9 and supplied to the voltage controlled oscillator 2 as a phase control signal. To explain the operation of the circuit configured in this way, the circuit other than the part surrounded by the dashed-dotted line in Fig. 2 is the same as the conventional dual circuit, so its basic operation is the same. be. That is, input signal eiM, in-phase and quadrature reference carrier eRI%eRQ, in-phase and quadrature detection output e1%e
Q, multiplied signal vr, clock signal frequency divided by two v summer, vQ
, vc, and the error signal v2 are as shown in equations (11 to 00). Next, consider the outputs el', e(,' of the discriminators 10 and 11. First, the input signal e of the discriminators 10 and 11 is
Consider the case where the phase error θe included in I and e(1 is zero (carrier synchronization is established). Figure 3 is a signal waveform diagram for explaining the operation of this circuit. When the phase difference is zero, each Discriminator human power vl, V4, el,
eQ and discriminator output e! ', eQ' have waveforms shown by solid lines in FIG. 3, respectively. However, the signals el, eQ
The initial phase of is set to 0° or 180°, and when the mark signal or space signal is continuous, the input signal el is identified at the rise/fall time of VQ. ', eQ' information pattern (a' to f') i detection output el-, C1q eye pattern information (a to f
) is delayed by a time of 1. If the phase error of the first-order ie,... is not zero □ □ 6o0. 1.1 □ 1θ・1〈-: If so, the information will not be mistakenly identified, and in this case, the discriminator outputs 01' and -0' will be constant information without being affected by the phase error θe. The pattern (a' to f') force j is obtained. Although the signal is delayed by the time T by passing through the signal i discriminators 16 and 11, the influence of the phase error θe is completely eliminated. Therefore, the output signal from the discriminator 1o and it' (71) is expressed as e summer', 8°. These two output signals eI' and eQ'
When multiplied by the multiplier 14, the multiplied signal ■1・'bavr'=
e Summer'・eQ'Mm6h6゜j,,,'-------=,("°゛On the other hand, when the frequency-divided signal vc outputted from the clock regeneration circuit 7 is inverted through the inverting path 15, its The signal ■c' is
. □ Jo・=-We,"=-CO3' hr (Yo. 1 'r'-cos(&(-th -1--
becomes. When these two signals vc' and vr' are multiplied by the multiplier 16, the output signal ve' of the multiplier 16 is VC=Vr
'・■c' 11-----(15) On the other hand, the signal VeT obtained by delaying the error signal ■e output from the multiplier 8 by a period of time '1'' in the delay circuit 17 is as follows: ■ v e7 = ---s in (2θe)fi ・------- -(1G). Should we reduce this? ! :v from VQT by tl13
When e' is subtracted, the signal νL becomes f at the output of the subtracter 18.
jF,] y, =vo7-ve---- sin (2θe)6 · sin Oe -----1 · -(17). Here, the first term of this equation (17) is the same as the conventional device (a DC component with phase error information, and the second term is an unnecessary AC component. However, this equation ('17) and the conventional device Comparing Equation (10) for the example device, it can be seen that the DC component is exactly the same, but the AC component can be reduced to almost zero in Equation (17) when θe''-0. In other words, According to the present invention, when the general transmission synchronization is established, the alternating current component is sufficiently suppressed, and the phase shift of the reproduced reference general transmission wave is significantly reduced. The frequency spectrum of the reference carrier wave reproduced using the method is compared with that of the conventional method by actual measurements.The ttIi characteristic shown by the solid line in FIG. 4 is the case according to the embodiment of the present invention, and the broken line is the characteristic of the conventional example. As can be seen from this figure, according to the present invention, the phase noise of the recovered carrier wave can be made extremely small, and the recovery AD characteristics can be greatly improved, especially when the reception level is low. According to the invention, the phase difference ((sound) of the reproduced carrier wave can be made extremely small, so that the fjj 8m characteristics are improved.Also, even when the bandwidth of the loop filter 9 is widened, the reproduction carrier wave due to unnecessary AC components Since the increase in phase noise is small, it is possible to significantly improve the synchronization characteristics of the carrier-locked loop as a result.Although the above explanation took an ideal MSK signal as an example, the present invention It is not only applied to pure MSK signals, but also has characteristics in the phase shift characteristics - U・Ta l' SK (Sinusoidal IN SK) and GM S with baseband limitation in the transmitter. K (Ga
ussianFiltered MSK) '1” F
M (Tamed Frequency Modu-
It can be widely used in digital frequency modulation systems with a modulation index of about 0.5, such as the 1.0-1.0.1 (Iation), etc., and can obtain two-sided effects. In addition, in the explanation of FIG. 2, the operation was explained in the case where the multipliers, delay circuits, subtracters, etc. were configured with 1/3 of the analog I:J circuit. is configured with an exclusive OR circuit, delays 11 and 19 are configured with shift registers, and instead of the subtracter 18, binary quantized signals ve'r and ■e' are used. On the other hand, if a logic circuit (not shown in the table) that outputs a three-value quantized signal according to logic is provided, the same effect can be expected without using the analog 1-I circuit. , in the second I, an inversion circuit 15 is inserted between the clock recovery circuit 7 and the multiplier 16, and this inversion circuit 15 will be For example, instead of inserting it between the clock recovery circuit 7 and the multiplier 1G, it may be inserted at the output of the multiplier 16. Alternatively, it may be inserted between the multipliers 14 and 16. Also) good. [Effects of the Invention] As explained above, according to the present invention, the configuration is simple because the operations necessary for the intercarrier period are performed in the base band. This circuit can easily be made into a monolithic IC. Furthermore, an MSK synchronous detection demodulator with good demodulation characteristics and synchronization characteristics can be obtained. Therefore, it is extremely effective especially when applied to digital mobile communication systems and satellite communication systems, which are expected to develop in the future.

[Brief explanation of the drawing]

FIG. F is a block diagram of a conventional MSK synchronous demodulator. FIG. 2 is a block diagram of an apparatus according to an embodiment of the present invention. FIG. 3 is a signal waveform diagram showing the time relationship of signals. FIG. 4 does not show an example of measurement of the frequency spectrum of the reproduced reference carrier wave. 1... Reception signal input terminal, 2... Voltage controlled oscillator,
3.4... Phase comparator, 5.8... Multiplier, 6...
- Timing information input terminal, 7... Clock regeneration circuit, 9... Loop filter, 10.11... Discriminator,
12... Data reproducing circuit, 13... Demodulated data output terminal, 14.16... Multiplier, 15... Inverting circuit,
17...Delay circuit, 18...Subtractor. Patent Applicant Nippon Telegraph and Telephone Public Corporation Agent Patent Attorney Nao Ide Takao

Claims (1)

[Scope of Claims] (]) A first phase comparator having one input as a phase continuous digital peripheral frequency received signal and the other input as the regenerated +U transmission wave of the received signal; a second phase comparator which has a received signal as one input and a signal whose phase is 90 degrees different from the 1M transmission wave as the other input; (a) a circuit that obtains demodulated output from output signals of different phases; (a) a first multiplier that receives the output signals of the first and second phase comparators as two inputs; and (ii) a timing clock for the received signal. a circuit that generates a clock signal whose frequency is divided by two, and a second multiplier which multiplies the signal obtained from the output signal of the first multiplier by the clock signal whose frequency is divided by two; A circuit that generates an error signal based on the signal outputted from the output of the second multiplier, and a circuit that generates the carrier wave using this error signal as a phase control signal so that the level of the error signal d is minimized. Synchronization of the digital frequency modulated signal with the resulting carrier recovery circuit tn 1! +
In one device, the circuit for generating the error signal includes a delay circuit that provides a predetermined delay to the output signal of the second multiplier; A third multiplier which receives as two inputs regenerated output signals having mutually different phases of 90 degrees obtained by identifying and reproducing output signals having different phases of 90 degrees, and an output signal of this third multiplier and the above-mentioned 2-fold multiplier. Synchronization of digital frequency modulation signals, characterized in that the circuit includes a circuit for obtaining a signal multiplied by an inverted signal of a clock signal, and a circuit for obtaining a difference between the output of this circuit and the output signal of the delay circuit. Modulator. (2) A synchronous demodulator for a digital-frequency modulated signal according to claim (1), wherein the circuit for generating the carrier wave includes a voltage controlled oscillator.