JPS6073376A - Board testing equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] This paper concerns improvements to the current board testing equipment.

(Prior art and its problems) A test signal is transferred in one step to a manual pin (not shown) of the board under test 5 via the write channel 3. Next, in the read mode, the output pin (
Read the output signal appearing on channel 4. (not shown). Lead through ink face 2. Next, the read result is compared with the correct value created based on the rough idea, and it is determined whether or not there is a problem.

Here, since the test board 5 has 300 pins in total for the two outputs,! When using a 3-bit CPU, 38 times per step of the test signal (300/8 = 37.
5') data transfer between the CPU and the board under test is required. FIG. 2 is a detailed view of the light channel 3 of FIG. 1. 31 to 338 are each 8-bit channels, 7 is an 8-bit data bus, 8 is a channel switching signal, and the same applies to the read channel. Data sent in 8-bit units from the CPUI is transferred to channel 31 by a channel switching signal.
From channel 3380F, F is set to +111it.

Data transfer between the CPUI and the board under test 5 is controlled by the program, so the transfer speed is low.

This is done 38 times for each stenog, so the board output signal is a slow roar that is far different from the actual operation.
Because the waveform has a long period, it is not possible to check the operation while observing the waveform with a synchroscope, etc.

(Purpose) In order to eliminate this drawback, the present invention has a memory that can store all steps of the test take and the output of the board under test for each step, and the conventional
Write between U and the board under test.

Instead of reading, I first wrote all the steps of the test I/take to the memory, and then wrote the write I/I between the memory IJ4 and the board under test without going through the CI).

Increase the transfer speed by reading and reading continuously.
-It's a good thing.

(Example) An embodiment of the present invention will be described below with reference to FIG.

6 is a disk memory for storing the test take; 9 is a write memory section that can store all steps of test data; 10
1 is a read memory section capable of storing all steps of board output in response to a test signal; 3' is a write channel; 4' is a read channel; 11 to 14 are 8-bit data buses, and 15 is a start signal from CP IJ.

16 is an end signal from the read memory section.

This operation will be explained below.

CPIJIJi, read the test take from the disk 6 and store it in the write memory 9 at the exit. When all steps of the test data have been stored, CPtJl outputs the start signal 15.
This starts the transfer of the test take from the write memory 10 to the manual pins of the board to be tested via the write channel 3'. This data transfer.

Perform all steps consecutively.

At the same time, the output signal appearing at the output pin of the board under test is stored in the read memory 10 via the read channel 4'. When the read memory 10 has finished storing all steps of the output signal, it outputs an end signal 16 for CP[Jl.
return it. Upon receiving this signal, CP [Month is lead memo January 0]
From there, the output of the tested board in response to the test data is read out and compared with the correct value created in advance to determine whether there is a defect.

When observing the operation of the elements in the substrate using a synchroscope or the like, after all steps of reading the test data in the write memory are completed, the process immediately returns to the first step and repeats reading again.

(Effects) With this invention, once a test take has been written to the write memory section, the ride read to the board under test can be performed continuously between the memory and the board without going through the CPU, significantly increasing the transfer speed. It is possible to observe the operation of the elements inside the substrate using a measuring instrument. Furthermore, since C'l)U does not intervene during write l)-do, there is a side effect of reducing the burden on CP[J.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the conventional device; Figure 2 is a detailed block diagram of the light channel 3 in Figure 1; Figure 3 is a block diagram of the embodiment of the present invention; 2
is an interface, 9 is a write memory, 10 is a read memory, and 3.3' is a write memory. 4.4' is a lead channel, and 5 is a board to be tested.

Claims (1)

[Claims] In a board testing device that manually inputs test data from a central processing unit to a board under test, reads the output of the board in response to the test data into the central processing unit, and checks for defects by comparing it with a correct value created in advance, A write memory capable of storing all steps of test data and a read memory capable of storing all steps of the output of the board corresponding to the test data are provided between the central processing unit and the board under test. A board testing device characterized in that transfer is performed between the memory and the board under test.