JPS60735A - Formation of electrode - Google Patents

Abstract

PURPOSE:To improve the step converage of an insulating film such as SiO and the like to be deposited after formation of an electrode by a method wherein a layer having a high etching rate is formed by performing an ion implantation on the surface of an electrode layer such as polycrystalline silicon and the like. CONSTITUTION:A polycrystalline silicon 3 to be turned to an electrode is formed on an Si substrate or an SiO2 layer 10 by performing a CVD method. Impurities such as phsphorus or arsenic are ion-implanted into the polycrystalline silicon 3, and a damaged layer 30 is formed on the surface thereof. Resist 4 is adhered on the damaged layer 30, a patterning is performed thereon, an isotropic etching is performed on the damaged layer 30 using the resist film 4 as a mask, and the isotropic etching is continuously performed to a point located in the midway of the polycrystalline silicon 3. Then, an isotropic etching is performed on the substrate or the SiO2 layer 10 by performing a reactive ion etching, and the resist 4 is removed. As a result, a tapered etching wherein the etchings in lateral and downward directions are equal can be performed, thereby enabling to prevent the generation of recessed parts when an insulating layer is deposited.

Description

DETAILED DESCRIPTION OF THE INVENTION Unexploded BA relates to the method of forming electrodes made of polycrystalline semiconductors used for the electrodes and wiring portions of MO8 structure transistors, and in particular, when etching the electrode layer when forming the t-electrode, taper etching is performed. The present invention relates to a forming method.

In MO8FETk, the silicon gate whose electrode is made of polycrystalline silicon is self-aligned and is suitable for miniaturization.

On the other hand, reactive ion etching, which is used in the VLSI manufacturing process, is a means of miniaturization.
Ion etching (RIE) equipment is commonly used and is an anisotropic reactive ion etching.

FIG. 1 shows an electrode formed by RIB, with a gate oxide M2 formed on a silicon substrate 1 and a polycrystalline silicon 3 formed thereon. Further, a patterned resist 4 is attached to the polycrystalline silicon 3, and anisotropic etching is performed by RIH using the resist 4 as a mask.

The resulting side surfaces stand vertically as shown in the figure, making it possible to form finer transistors and wiring. However, on the other hand, the wiring after forming the ta electrode in Figure 1! When 5i02 or other insulating film is deposited on the surface by CVD to insulate the poles, S I Ch
At 5K, a concave portion is formed in the middle of the polycrystalline silicon electrode &3. This is usually expressed as poor step coverage, and in order to improve this step coverage, a third
As shown in the figure, a silicon substrate or SiO2 layer is first etched by isotropic etching.

There is a method in which the surface of the polycrystalline silicon 3 formed above is subjected to Taber etching, and then vertical etching is performed by RIE.

However, although the etching is isotropic just below the resist 4, the etching layer in the lateral direction due to the resist 4 is usually reduced to 60 to 80 inches, and therefore the taper angle in the lateral direction is as shown in the figure. Vertical direction is 0.7:1.
If the value is as small as 0, the step coverage will not be improved very much.

Therefore, the present invention has been made in order to improve the above-mentioned problems.In order to control the taper angle of etching, a layer with a fast etching rate, such as a polycrystalline silicon layer, is provided on the surface of the electrode layer. The present invention relates to a method for forming an electrode, which improves the step coverage of an insulating film such as SIO, which is deposited after electrode formation, and improves the yield.

Embodiments of the present invention will be described below with reference to process-by-step diagrams shown in FIGS. 4a to 1@4f.

First, polycrystalline silicon 3 is formed on a silicon substrate //1sso2y=xo by CVD.

Then, phosphorus or arsenic impurities are ion-implanted into this polycrystalline silicon 3 at a dose of 1×e-2 10 at an acceleration voltage of 60 keV to form a damaged layer 30 on the surface (fourth
Diagram a). The damaged layer 30 is also formed shallower than the layer to be tapered etched in a later step. Furthermore, the introduced impurities are later used as carriers.

Next, a resist 4 is applied to the surface and a predetermined patterning is performed (FIG. 4b). Then, using the resist 4 as a mask, the damaged layer 30 is isotropically etched (FIG. 4C), and then isotropically etched deeper than the damaged layer 30 to the middle of the polycrystalline silicon 3 (FIG. 4C). d). after that,
Silicon substrate or S i OxMlo by RID
Anisotropic etching is performed up to this point to form vertical side surfaces (Fig. 4e). Finally, the resist 4 is removed to obtain an electrode (FIG. 4f).

Next, the principle of the present invention will be explained.

Now, when the inclination angle of the taper etching is 45 degrees and the downward etching rate ratio of the damaged layer 30 with a fast etching rate and the polycrystalline silicon layer 3 with a slow etching rate is 2 koL, the following is shown in Fig. 4. As shown, when taper etching the damaged layer 30, if the downward direction is set to 1.0,
In the lateral direction, it is etched at a speed of 0.7.

Next, as shown in FIG. 4, when taper etching the polycrystalline silicon 3, the etching speed is slow at 0.5 in the downward direction, while the etching rate in the lateral direction is kept at 0.7, which is the same as in the previous process. ing.

Therefore, the lateral etching attack that was delayed when etching the damaged layer 30 in the first half is covered when etching the polycrystalline silicon 3 in the second half, and taper etching is completed to the desired depth in the middle of the polycrystalline silicon 3. When this is done, the amount of etching in the lateral direction and in the downward direction is equal, resulting in taper etching of approximately 45° as shown in FIG. 4d.

FIGS. 5a and 5b are electron micrographs of polycrystalline silicon 3 shown in FIG. 4d when isotropic taper etching is performed to a desired depth, and the upper semicircular shape is resist.

In the above embodiment, polycrystalline silicon is used as the electrode material, but electrode materials such as Mo5i2 (silicide) and 7k1wTa may also be used.

In addition, in the above explanation, an example was shown in which the taper angle was 45° and the etching rate was Q, 7:1.0 and 0.7:0.5, but the profile of the damaged layer (impurities, damage)
is closely related to taper angle control, and is not particularly limited.

As described above, the present invention makes use of the phenomenon that a layer damaged by ion implantation is etched faster, and by creating a difference in etching rate between the surface layer and the surface layer, a sufficiently tapered surface can be obtained. Therefore, it is possible to prevent the formation of recesses when depositing the insulating layer, and it is possible to improve the yield especially in VLSI and the like.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a conventional electrode by RIE, FIG. 2 is a cross-sectional view showing a state in which an insulating layer is deposited on the electrode in FIG.
Figure 3 is a sectional view showing an improved conventional electrode, Figure 4a
4f to 4f are cross-sectional views of each step of the forming method according to the present invention, and FIGS. 5a and 5b are electron micrographs of the cross-sectional views in the step of FIG. 4d. 10...Silicon substrate or S i O, layer 3
...Polycrystalline silicon 30...Damaged layer 4...Resist patent applicant Pioneer Corporation Fig. 1 2 iJi3 Fig. 0- (a) 3 to 10 and 7 fO/ '- 3 ~ fO' Fig. 4 fOβ t5 (O) Procedural amendment export/export) 1988 Patent Application No. 108375 2 Title of the invention Method for forming electrodes 3 Person making the amendment Case related to the patent Applicant address: 1-4-1 Meguro, Meguro-ku, Tokyo 153 Name (501) No\ia J-Nia Co., Ltd. 4, "Detailed description of the invention" column 1 of the specification subject to amendment, Specification @ 2 Page 5 line r,, Etchir(1,, J is corrected to [1, Etching, , J. " to "80 Anisotropic etching with reactive ions 0." I will correct it.

Claims (1)

[Claims] A step of forming an electrode layer on or on a semiconductor substrate, a step of forming a damaged layer on the surface of the electrode layer by ion implantation, and a step of depositing a resist on the damaged layer to form an electrode pattern. A method for forming an 11L pole, comprising: a step of isotropically etching the damaged layer exposed by patterning, a step of isotropically etching up to the middle of the electrode layer, and a step of anisotropically etching the remaining electrode layer.