JPS6074032A - Microprogram controller - Google Patents

Abstract

PURPOSE:To improve reliability without deterioration in processing performance by making a majority decision when accessing a control word which disables retrying by microinstructions and entering a branch mode in other cases. CONSTITUTION:When an address for accessing a control memory (CS) 2 is set in an address register (CSAR) 1, control memories #1-#4 of CS2 are accessed simultaneously to output four control words. Processing for reading or arithmetic based upon read data can not be retried, so a branch mode signal is turned on and one of branch selection signals (e.g. a) is turned on in this case to fetch and set one of the control words of CS2 in a data register (CSDR) 4. When an arithmetic result is stored in a register, a majority decision mode signal is turned on since the retrying is impossible and a majority decision among the outputs of the memories #1-#3 of CS2 is made to set the result in CSDR.

Description

Detailed Description of the Invention fa) Technical Field of the Invention The present invention relates to a microprogram-controlled data processing device having a plurality of control memories, in which the outputs of the plurality of control memories are extracted by majority logic. This invention relates to a control method that selects one item and takes it out.

Noboru J. Background of the Technology Recent data processing devices are moving towards adopting a control system using microprograms, in anticipation of the trend toward lower prices of memory due to the remarkable progress in semiconductor technology, and the flexibility of control methods.

However, if we analyze the operation of the control memory section of a microprogram-controlled data processing device in detail, we find that one macro instruction is executed by executing a plurality of control words.

Therefore, even if a call occurs in the read control word or related 11 old Raku, depending on the type of macro instruction, the error that occurs before the execution of a certain control word can be resolved by the system by retrying the instruction by hardware. It is possible to avoid downtime, but if the above control word (till, 1111) fffll an ) +2 that changes the source data
R' (Retry may not be possible for an error that has occurred, and there is a risk that the data processing device will go down.

In a data processing device controlled by a microprogram, there is a need for a method to avoid the above-mentioned problem that makes it impossible to read macro instructions at the control word level, economically and without reducing processing performance. Ta.

Regarding the error in the control word itself, for example, the service processor retains all the control words for initial microprogram loading, so the corrective writing method is not the problem; the problem lies in the macro instruction. The problem lies in how to deal with the case where an error occurs in the control word that makes it impossible to try again at the level, and the present invention solves this problem.
This is an attempt to avoid this without using error correction code logic (ECC) and without increasing hardware too much.

(C) Conventional technology and problems Conventionally, error checking for ff1lJ words that has been generally adopted is error correction code logic tJlltl (hereinafter E
However, in order not to reduce the processing performance of the data processing device, the controlled unit is controlled using the control word (the control word itself read from the control memory) before being modified by ECC1. was.

Therefore, when an ECC error is detected, 1ffl is always tried for each macro instruction, but for some macro instructions, when a certain control word is executed, the source data (from the program) is already processed. There are cases where it is impossible to retry instructions using hardware due to changes in visible registers or data in main memory.There are ways to improve reliability by -1 without using instruction retry. was necessary.

Furthermore, if the controlled unit is controlled using the data corrected by ECC, the machine cycle will be reduced in a microprogram control mechanism where the next microprogram address is determined by the read control word itself. There is a problem in that this increases the processing capacity of n;7 and lowers the processing capacity of J:).

fd) Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention provides a microprogram-controlled data processing device that is provided with a plurality of control memories and uses a majority logic mechanism and a branch mechanism to use the output data. The object of the present invention is to provide a method that can improve overall reliability at high speed and economically.

(e) Structure and object of the invention According to the present invention, in a microprogram-controlled data processing device having a plurality of control memories, a control memory for storing a control word and an address for accessing the control memory are provided. a selection circuit that selects one of the plurality of control words read simultaneously from the plurality of control memories, and a data register that holds the output of the selection circuit, the selection circuit comprising: The first mode selects and outputs one of multiple inputs using an external selection signal, and the second mode provides a method of selecting and outputting a matching input from multiple inputs. This is achieved by performing a check using majority logic for control words that cannot be retried if an error occurs when a certain control word is executed, and fast branching for other control words. Since the processing is controlled to enable processing, it is possible to improve reliability and suppress a decline in processing capacity without significantly increasing the amount of hardware.

(fl Embodiments of the Invention First, to summarize the gist of the present invention, the present invention is limited to control words such that if an error occurs when a certain control word is executed, it becomes impossible to retry the instruction. When processing these control words, access to the control memory should be in majority mode, so that even if one control word causes an error, the system is not affected, and other control words are When processing, the branch mode is intended to enable high-speed one-mike one-bump one-nogram branching as in the past.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram explaining the present invention in detail, and FIG. 2 is a block diagram showing one embodiment of the present invention.

First, the present invention will be explained in detail with reference to FIG. This figure shows the flow of processing in a microprogram-controlled data processing device. Data is read at the stage indicated by ■, arithmetic processing is performed on the data at the stage indicated by ■, and At the stage indicated by , processing is performed to store the calculation result in a general-purpose register, etc., and a plurality of control words are executed at each stage.

Therefore, the execution of control words that make it impossible to write macro instructions related to the present invention is limited to control words that are executed at step (2), where there is a possibility that the source data may be changed. The majority logic is used only for the control word readout executed in . Regarding the reading of the control word executed at the stage ■■, error detection is done with a parity check, and when an error occurs, the corresponding macro instruction is retried to prevent the data processing device from going down. Control.

Further, since the microprogram branch is performed by detecting an overflow of the calculation result, all "0", etc., it can be limited to the stage (2). Therefore, at least the reading of the control word executed at this stage is performed in the branch mode.

However, since reading in branch mode is controlled so as to select and read one of the outputs from a plurality of control memories, it is not necessary to use it only for so-called microprogram branch processing; When the control words necessary for executing a macro instruction are stored in a distributed manner in multiple control memories, these control words can be read out sequentially by using the lower bits of the microb I cogram address as a selection signal. Since the branch mode described above can also be used for reading out general control words, it is understood that the branch mode can be used for reading out the control words executed at the stage (■).

The present invention aims to provide the most effective microprogram control method by paying attention to the fact that the execution of the control words at each stage has different effects on the system.

In order to improve the reliability of the control memory system, we adopted a majority logic mechanism, and in order to not reduce processing performance, we tried to provide a high-speed branch function, but three controls were required to perform the majority logic. If a memory is required and an attempt is made to provide a high-speed N branch function, 3N control memories will be required, which would be impractical.

When the present invention is implemented, by configuring the majority logic mechanism and the fast branch mechanism so that they can be used depending on the control word, it is possible to realize the same function as described above by using N control memories. That's good.

Hereinafter, the present invention will be explained in detail with reference to FIG. In the figure, 1 is an address register (C5AR), 2 is a control memory (CS), 3 is a selection circuit composed of AND circuits 31 to 38 and an OR circuit 39, and 4 is a data register (C3DR).

In this embodiment, four control memories (CS) 2 are provided in consideration of realizing a high-speed four-branch function.

First, the address for accessing the control memory (CS) 2 is stored in the address register (C5AR) 1, and when the control memory (C'S) 2 is accessed, the four addresses #1 to #4 are stored. The control memory is accessed simultaneously and four control words are output.

The above four control words are selected by two mode signals (i.e., majority mode signal and branch mode signal) and a branch selection signal, and one of them is selected (iU, when in majority mode ↓, For example, control is performed to extract a matched control word outputted from any two control memories.

Now, looking at the case of branch mode, for example, when the branch mode signal is turned on and the branch selection signal a is turned on, as is clear from the figure, the AND circuit 31 is gated and the #1 control memory ( The output of CS) 2 is selected, passes through the OR p1 path 39, and is input to the data register (C3I]R) 4. If this control word is the branch destination control word, a fast branch has been executed. The control word that is controlled by this high-speed zolanthi is the control word that is read out at stage 2 in FIG.

In addition, in the case of majority mode, since the majority mode signal is on, the AND circuits 32 and 34 are activated by this signal.
．． 36.38 is gated, and the matched output signal of the two control memories (C3) 2 input to one of the AND circuits is selected and sent to the OR circuit 3.
9 to data register (C5DI?) 4.

In this embodiment, the majority logic is used in which it is only necessary that two of the three output signals match, so the control memories #1 to #3 are accessed and the data is read from #3. Even if the output control word is faulty, if the outputs of control memories #1 and #2 are normal, a matching output is obtained in the AND circuit 32, and the data register ((:5DR) is output through the OR circuit 39. The control word is set to 4,
The data processing device can operate correctly. The control word that is controlled by this majority logic is the control word that is read out at stage 3 in FIG.

tg) Effects of the Invention As explained in detail above, when the microprogram control device of the present invention accesses a control word that makes it impossible to perform a 1' line with a macro instruction, the control word is accessed in the majority mode; When accessing a control word that can be tried using a macro instruction, the branch mode is controlled to enable high-speed microprogram branching, improving reliability without significantly increasing the amount of hardware. This has the effect of reducing processing power and preventing a decrease in processing capacity.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the present invention in detail, and FIG. 2 is a block diagram showing one embodiment of the present invention. In the drawing, 1 is an address register (C5AR), 2
is the control memory (C3), 3 is the selection circuit, and 4 is the data register (CSDIol).

Claims (1)

[Claims] In a microprogram-controlled data processing device having a plurality of control memories, a control memory for recording a control word and an address register holding an address for accessing the control memory, and a control memory for recording a control word and an address register for holding an address for accessing the control memory, and a It has a selection circuit that selects one of the plurality of control words to be read out, and a data register that holds the output of the selection circuit. In the first mode, the selection circuit selects one of the plurality of control words by an external selection signal. A microprogram control device characterized in that any one of the inputs is selected and outputted, and in a second mode, a matching input is selected and outputted from a plurality of inputs.