JPS6074074A - Priority control system - Google Patents

Abstract

PURPOSE:To improve processing performance by adding a priority to a request inputted to a buffer memory in addition to the priority of a system. CONSTITUTION:Requests A and B inputted from systems A and B are stored in buffer memories A and B through paths 21-1 and 22-1. Request numbers from a counter 15 for request numbers are added to data on those requests when those requests are stored. When a processing part 14 gets ready to accept a new request input, an indication is inputted to a priority circuit 13 through a path 14-2 and also inputted to a readout counter 16. The readout counter 16 sends the next request number following requests which are processed so far by the priority circuit 13 to comparing circuits 17 and 18 according to the indication of the processing part 14, and they are compared with request numbers read out of the buffer memories A and B on FIFO basis to confirm coincidences of the numbers, thereby inputting comparison output signals CMPA and CMPB to the priority circuit 13.

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention Grand Duchess Day and Moon, F4 Sound Access? kll 4 body parts
This is related to the control of the ranking of cattle.

(b) Background of the technology In recent years, with the development of LSI, it has become possible to mount central processing units other than electronic calculations (depending on the content) on a single printed board. It has become common for a plurality of systems to be interconnected to form one system, and a plurality of such systems share one main memory unit (hereinafter abbreviated as MMU) and use it as a child computer in a temporary multi-configuration.

Main memory access G, tll (ill device (hereinafter referred to as MAC)
MAC is a device that controls access from the system with 1'M shared MMUs in the multi-configuration electronic computer, and the MAC handles processing requests (hereinafter referred to as requests) input from each system. A buffer memory provided corresponding to each system temporarily stores data (hereinafter referred to as "abbreviation"), and processing requests generated from the buffer memory are processed preferentially according to a system processing order assigned in advance to each system. It consists of a priority circuit, etc.

In a multi-4R electronic meter 3I, each system has a wide variety of requests, and how the MAC controls these is an extremely important issue as it relates to the overall processing performance of the computer. be.

(c) Prior art and problems Figure 1 shows two sets of systems as an example.
A system diagram shows the circuit configuration in which inputs to the AC are used to control the selling order. Figure 2 shows the circuit configuration in which inputs to the AC are performed to control the order of sales. When the processing section of the MAC is busy working on other tasks and does not accept new input requests, A time chart shows a situation in which a request is input from the system and is temporarily stored in the buffer memory. FIG. 3 shows that as a result of the process according to the time chart in FIG. indicates system B. 10 is a part of the MAC; 'Og1' shows the times related to controlling requests from each system that are input to the MMU/'34'f4
composition is shown. 11 is a buffer memory IJA, 12 is a buffer memory B, 13 is a priority j-order circuit, and 14 is a processing section.

System A 21. Requests output from system B 2-2 are sent to buffer memory A 11. through paths 21-1 and 22-1, respectively. Input 12+ buffer memory B. The buffer memo IJA, B uses a first-in, first-out method (also referred to as first-in first-out, hereinafter referred to as FI).
(abbreviated as FO). Priority circuit 13
is a register that outputs requests to the processing unit 14 according to the priority order set in advance in the system. For example, processing of a request from system A (hereinafter referred to as request A) has a higher priority than processing of request B. Then, requests A and B input to the cylinder tip priority circuit 13
first outputs request A, then outputs request) B. Therefore, when a request is input to the circuit 13 from the buffer memories A and B, requests are again outputted from the circuit 13 in the order of buffer memories A and H.

The output from the priority circuit 13 is input to the processing unit 14 via a path 13-1, processing is executed, and based on the processing, the MMU is accessed via a path 14-1.

In FIG. 2, cycles 0 to 6 indicate timing cycles by clock pulses for buffer memory writing and register operations in FIG. When A and B are input to MAClo as shown in the figure, the buffer memory A
The requests are stored in the buffer memory 11 and the buffer memory 12 at one cycle intervals as shown in the figure.

FIG. 3 shows the buffer memory IJA as a result of the circuit operation in FIG.
, the state in which requests are temporarily accumulated in B is shown in 11-1.1
It is shown in 2-1. Busy state of processing unit 14 (cycle θ~
When step 5) is completed and cycle 6 begins (t Al and Bl are outputted to the processing unit 14 in the order of A1→B1, and if the processing unit 14 is not busy after that, they are outputted sequentially, and the processing unit 14 is outputted in the order of A1→B1→A2→B2→A3.
It is output to and processed.

The control according to the above-mentioned conventional technology is characterized in that the requests of each system temporarily stored in the buffer memory are outputted fairly in the order in which the buffer memory received them, for example, in the order of A and B, as shown in FIG. As mentioned above, even if it is originally desired to prioritize requests 1.2.3 of request A, there is a problem in that request B intervenes as described above.

Cd) Purpose of the Invention In view of the above-mentioned problems, the present invention provides a main memory access control device that has a buffer memory and prioritizes requests input from a plurality of systems, in which a series of requests from a specific system is prioritized. The purpose is to process the information quickly.

(a) OY construction of the invention The present invention is capable of processing processing requests to the main memory from a plurality of systems of a computer by temporarily storing them in a buffer memory provided corresponding to each of the systems for waiting for processing. In a main memory access control device that reads the processing request from the buffer memory and executes the processing according to the system processing order set for each of the systems,
A processing request received by each of the buffer memories is assigned a ranking number at the time of reception, and the processing request is read from each of the buffer memories according to the j-place number, and when each read output has the same -j song-order number. The system executes processing according to the system processing order, and the above object is achieved by the present invention.

(f) Practical example of the invention FIG. 4 shows an example of priority control according to the present invention in a system diagram, taking as an example the case where the number of systems is two, similar to FIG. 1 of the prior art. Figure 5 shows a time chart of the state in which each circuit in Figure 4 operates in response to a request.
FIG. 6 shows the state of requests temporarily stored in the result buffer memory shown in FIG.

In FIG. 4, the same reference numerals as in FIG. This is a sequential circuit, and the newly provided circuit according to the present invention is 1
5 request number counter, 16 read counter, 17 comparison circuit A, and 18 comparison circuit B.

The present invention determines the order of use of the system as before,
In addition, we are trying to add 1F1 (priority to each request temporarily stored in the buffer memory) to this,
The following will be implemented.

Requests A and B input from systems A and B are
As shown in Figure 4, the data is stored in buffer memories A1-1 and B12 via paths 21-1 and 22-1. At the time of this storage, a request number is added to the data of each request by the request number counter 15. The request a counter 15 (abbreviated as RQ) is a count register that repeatedly adds 1 to a number corresponding to the memory capacity of the buffer memories A and B in order.

When the processing unit 14 is in a state to accept a new request input, the instruction is sent to the first priority circuit 1 via the path 14-1.
] and input it to the anti-lift counter 16.

The read counter 16 (abbreviated as NEXT) is a counter that forms the same number as the request number counter 15, and in accordance with the instruction from the processing unit 14, it reads the requests processed so far in the priority circuit 11. Send the next request number to comparison circuits A 17 and B 18, and
The request numbers are compared with the request numbers of the requests read out from the buffer memories A and B using the method 6, and after confirming that the numbers match, the comparison output and store names CMPA and B are input to the priority circuit 13.

1y Uni priority circuit 1-3 inputs CMPA and B, and C
The priority order is determined according to the request number and manually inputted to the processing unit, and if the CMPA and B numbers are the same, the system's direct order is determined as in the conventional method, e.g., A is output one time before B. 512th, the above-mentioned situation is shown in a time chart. The 0 processing unit 14 is busy up to the cycle 5, and during this time, when Riffnis) A and B are input as shown, the buffer memory A1! , B121, the μ request number 3 shown in the figure is added and stored.

1"-Figure 6 μ The request bar is stored in the buffer memories A and B, and the status of the quest is shown in 1]-1 and 1]-1, respectively. (Small) , - numbers indicate the added request numbers.) The priority circuit 1-3 first looks at the request numbers in Figure 6 and determines the order, and if the numbers are the same, it determines the order by placing A one hair ahead. Then, the output is performed to the processing unit 14 in the order of A1→A2→A3→B1→B2.

As described above, according to the present invention, liff varnish) A is processed with priority, and liff varnish) B is not interposed in the middle.

The inputs for requests A and B above are just one example, but
Suppose that the busy state of the processing section continues for even longer than in Figure 5,
Assume that the timing is such that the input is made after the request B has been input (corresponding to ref cycle 3). In the conventional technology, the input priority of requests A and B is completely ignored.
Requests A and B are processed alternately, but according to the present invention, the processing of request B is started after the processing of request A is completed, and the priority at the time of input of requests A and B is In the above example, the number of systems and therefore the number of requests is 2.
Although the case of a set of systems has been taken as an example, it goes without saying that the present invention is also applicable to a case where the number of systems is plural.

(g) Effects of the Invention In a main memory access control device that has a buffer memory and controls requests input from the +MH system, the present invention gives priority to requests input to the buffer memory in addition to system priority. The present invention allows a series of requests from the system to be processed with priority, and has an extremely large effect on improving the processing performance of the child computers.

[Brief explanation of the drawing]

FIG. 1 shows a system diagram of a conventional priority control circuit of a main memory access control device W taking two sets of systems as an example, and FIG. 2 shows a time chart of the operation of the circuit of FIG. 1, FIG. 3 shows the accumulation status of requests temporarily accumulated in the result buffer memory of FIG. 2. FIG. 4 shows a system diagram of an embodiment of the circuit configuration according to the 1-priority control method of main memory access system 1iDl installation according to the present invention, taking two sets of systems as an example, and FIG. A time chart showing the operation of each anastomotic circuit to which a request is input is shown, and FIG. 6 shows a state of accumulation of requests temporarily accumulated in the backup memory as a result of FIG. 5. The same symbols indicate the same objects throughout the figures, 11 and 1]
12 and 1''2 indicate buffer memories B of the conventional and present inventions,
13 and 1-3 show priority circuits of the prior art and the present invention,
14 is a processing unit, 15 is a request number counter, 1
6 is a reading counter. 17 and 18 are comparison circuits A and B, and 21 is a system A. 22 indicates system B. Fig. 1↓ M/jσ s 2 Fig./l-7 Fig. 4' /j MtJ Fig. 5 Fig. G

Claims (1)

[Claims] Temporarily storing processing requests from a plurality of systems of an electronic computer to a main storage device in a buffer memory provided corresponding to each system for waiting for processing, and reading out the processing requests from the buffer memory when processing is possible; In the main memory access control device that executes processing according to the system processing order set in each of the systems, a processing request received by each of the buffer memories is assigned a ranking number at the time of reception, and the processing request is assigned a ranking number of 1. Therefore, the priority control method is characterized in that the processing requests are extracted from each of the buffer memories by 11y, and when the read outputs have the same priority number, the processing is executed according to the system processing order.