JPS6074549A - Semiconductor device - Google Patents

Abstract

PURPOSE:To contrive to enhance the integration of a semiconductor device by a method wherein the gate metals of MOSFETs are extendedly disposed in the semiconductor device, wherein basic cells consisting of the MOSFETs are arranged in an array state and an artibrary logical circuit is constituted. CONSTITUTION:Extended gate metals 2', which have made to extend gate metals 2 linking to the gates of MOSFETs, are provided under a first-layer wiring enabled region A, which is used as a channel between basic cells, and the extended gate metals 2' are provided, covering the first-layer wiring region. According to such a way, connection of the gates of the basic cells and the first- layer wiring at the channel region adjacent to the gates of the basic cells can be performed without using a second-layer wiring. As a result, the region for the second-layer wiring can be more used by performing a wiring between unit cells, thereby enabling to effectively use the wiring region.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a MOS gate array mask slice LSI in which MOS gates are arranged in an array and an arbitrary logic circuit is formed by a wiring pattern.

In particular, the present invention relates to a semiconductor device that can be highly integrated by extending gate metal and wiring.

(2) Background of the Technology In recent years, with the development of MO3 integrated circuit technology, the number of elements within an LSI chip has increased, and various wiring systems within this chip have been proposed. Among them, St (silicon)
There is a method called a mask slicing method, which has a common process step that does not change depending on the type of LSI up to the level on the substrate, and in subsequent processes, the wiring can be changed depending on the type of LSI. In this mask slicing method, wiring within a unit cell constituting a basic logic gate and wiring between unit cells are performed using multilayer wiring layers.

Higher integration is possible by allocating wiring in each layer.

A gate array manufactured by this mask slicing method is an LSI in which cells are arranged in an array, wiring areas are provided between the cells, and input/output circuits are provided around the arrayed cells.

(3) Problems with the prior art The basic gates of the mask slice of a conventional CMOS gate array generally have a structure as shown in FIGS. It is called Basic Game) BC). Figure 1(a) shows the p-channel MOS FET (Field Eff
ect Transistor) Trca, Tr
a2 and n-channel MO3FET Tra 3, Tra
A basic cell BC in which a is arranged is shown. When wiring the FET, the gate G is formed by metal wiring.
a+ to Gaa are provided. Figure 1 (g)) is the first
The p-channel and n-channel FETs are arranged in the same way as in the figure (al).

One metal wiring is separated and the gate terminals are divided into two, Gb1 to Gb7. More than MOSFE
The composition of T is Tra + and Tra2+ and Tra 3 and T
ra 4 are connected in series, Trca and Tra3
+ The respective gates of Tra2 and Tra a are connected. and Trb+ and Trb2. Trb3 and Trb4 are connected in series, Trb+ and Trb
Each gate of Gbi-G is connected by metal wiring.
ba, Gb6. Also, Trb 2 has Gbi - Gba,
↑Gb for rbm! 1-Gbi is installed. 1st
Figure (C) shows P channel F[! ↑Trc + and Tr
C2, Tra3 and n-channel FETTrca + T
rca + Trca are connected respectively, Trca and Trca, Trc2 and Trca, Tra3 and Trc
s are connected to each other, and gate terminals Gc+ to Gca are provided. The gate metals are connected by metal wiring as described above. And both sides of the metal wiring are source (5 sources) + drain (drain).
).

Examples of logic gates constructed using the basic gate of FIG. 1(a) are shown in FIG. 2(al, (b), (e),
+d). Figure 2 (a), (bl, (C1)
, (dl is 2-man power NAND gate, 2-man power NO
It constitutes a logic gate consisting of an R gate, a 4-person NAND gate, two 2-person ANDs, and a 2-person NOR that inputs the output of the 2-person AND. Figure 2 (al), (
bl), (cl).

5- (dl) is shown in Figure 2 fa), (b), (C1, (
dl (7) Each logic gate circuit. These logic gate units will be referred to as unit cells UC. This unit cell is composed of at least one basic gate and exhibits a logic function.

still.

The 0 mark in Fig. 2 (al, (b), (cl, +d)) is the 5t-A7! contact hole C, which is used to connect the wiring between each wiring layer. In Fig. 2 Ta), Tb) The P-channel MO3FET Tr+ + Tr2 has a common drain D1, and 31.52 and 5
i-A I! A pattern for a power supply ■cc is provided through a contact hole C. On the other hand, n-channel MOS
FETTr3゜Tra is the drain D3 and T of Tr3
The source S4 of ri is common and B4 of Tra is Tra,
Connect to Dl of Tr2.

St-Aβ contact hole C to source S3 of Tr3
A pattern of a power supply Vss is arranged through the Vss.

Then, the gate terminals A + and B + are input and Try
.

Si from drain D3 of Tr2 and drain D4 of Tra
-Aj! Output X1 is taken out through contact hole C. This logical formula is: A NAND logic gate is configured.

Figure 2 (bl, (bl)) p channel MO3
FETTr6. Tra, n channel region S F E
The arrangement of TTrv and Tre is the same as in FIG. 2+a). And the source of FETTrll is 5t-A
The source of Tre is the drain of Trt, and the region forming the drain of Tre is Si −
Connected via A71 contact. Said 1'I
! The source of TTr7 and the source of Tre are 5i-Aj! in the pattern of power supply Vss! Wiring is done via contact hole C. And gate A2 where metal wiring is made
．． B2 is FETTrs and Trt, FETTrs and Tr
The respective gates of e are connected and serve as input terminals. Further, an output X2 is taken out from the drain of the FET Tri via a Si-AIl contact hole C.

Also, as shown in the figure, the output X2 is taken out from the common region which is the drain of the FET Trv and the drain of the Tre through the 5i-Aβ contact hole C. Therefore, the PET Tr! As a result of the wiring of l -T e, a two-manpower NOR (X 2 =A I +82) logic gate is constructed. Therefore this is input A2
．． When both B2 are "L", "H" level is output.

Under other conditions, "L" level is output.

Figure 2 (C1, (dl is p channel F E TTr9
~Tr+2.

The n-channel FETTr+ 3 to Tr+ a are shown in Figure 2 (
The BC shown in al. was used twice, and the 5i-
4-person NAN wired through AJ contact hole C
D (X3=A3・B3・C3・B3) is configured. The PET Tri and Tr+ s, FET Tr+
o and ↑yl 4, pET Tr+ + and Tr+ e
, the gates of FETTr+2 and Trys are respectively wired with metal and arranged so that inputs A31B3C3 and B3 can be taken out.

Output X3 is the FET Tro, Tr+ 21 Tr+
31” Tr, + a drain and FET Tr+ 6
The structure is as shown in the figure, in which the wiring is connected so that it can be taken out from the drain of the
As a result of the wiring, the logic gates have inputs A3. When B3°C5D3 are all at H" level, the output x3 is at L level, and under other conditions, the output is at H level.

Similarly to FIG. 2(e), in FIG. 2(d), Td), a P-channel FETTr+ t ~Tr2o and an n-channel FETTr2+-Tr2g are arranged, and the logical formula
A circuit represented by =A4.B4+C4.B4 is configured. AN to input the so-called I A a I B m
The configuration is such that the output from the AND gate that inputs the D gate, C4, and B4 is input to the NOR gate, and the output X4 can be taken out.

Although the example is shown above in which the logic gates of the four types of unit cells are wired, other logic gates may be constructed by changing the mask pattern and performing the wiring process. In the wiring process, the wiring layers are stacked and the wiring between each wiring layer is S^! Connection is made through contact hole C. On the other hand, LS I is a large-scale logic game that combines the input/output circuits for connecting the unit cell and the outside of the LSI.
It is formed by wiring a wiring layer on the C chip. This type of work is called a router. By arranging the large-scale logic gates as shown in FIG.
is configured.

In FIG. 3, in the gate array LSI chip, unit cells UC are arranged in an array, and around the unit cells are provided input/output circuits I10 necessary for connection with the outside, and furthermore, the input/output circuits 110 There are pads P around which will become terminals.
is sharply defined.

There is a channel region CH for wiring between the unit cells 00 arranged in an array, so that Al wiring can be formed.

Next, a specific example in which the CMOS gate array is actually wired will be explained with reference to FIG. In Figure 4.

Two rows of basic cells B consisting of basic gates
A plurality of rows of C are provided in parallel with channels in the wiring area as boundaries. The straight line shown by a solid line parallel to the basic cell BC arrangement in the channel of the wiring is the first layer Aβ wiring layer, and the wiring shown by a broken line crossing over the base 10-thick cells BC is the 2Nth wiring layer. This is an Aβ wiring layer. And the second layer wiring is
Used for wiring between unit cells.

No second layer wiring is used inside the unit cell. Here, the unit UC consists of multiple base thick cells BC.
It performs two logical functions.

Note that the O mark at the intersection or end point of the first layer wiring and the second layer wiring is a contact hole that connects the rewiring, and the O mark on the basic cell BC frame is the first layer from the second layer wiring. connection to the wiring or gate metal.

When wiring is performed using 1Nth wiring and 2nd layer wiring, as the scale of one circuit increases, the number of wiring also increases proportionally. ), and the length of each wiring also increases. Further, the increase in the number of wires places a greater burden on the router, increases the operating time of the computer, and has the problem of adverse effects such as an increase in unconnected wires and a so-called delay in connection. In addition, in response to the increase in the wiring area, a new wiring layer,
In other words, it is possible to deal with this by using a third layer of metal wiring, but as mentioned above, this also places a heavy burden on the router, making the VLSI mask slicing process more complicated, and reducing the VLSI fraction. There are problems that cause deterioration.

On the other hand, an effective measure against increasing the scale of logic circuits is to define the logic of unit cells in a larger manner and reduce the number of wires to be wired by the router. This concept can be applied not only to CMOS gate arrays but also to all logic VLSI. However, as the logic within a unit cell increases, the number of wires within it also increases, which has the disadvantage that it cannot fit within the basic gate and reduces the wiring area for the router, that is, the wiring area of the channel portion.

(4) Purpose of the Invention In view of the above-mentioned conventional problems, the present invention solves problems such as an increase in the number of wiring layers, an increase in the so-called mask layer, an increase in the number of process steps, and an expansion of the wiring area required in advance, that is, an increase in the area of the chip. It is an object of the present invention to provide a semiconductor device that can configure a gate array on a large scale without having to do so.

(5) Structure and object of the invention According to the present invention, in a semiconductor device in which basic cells made of MOS FBT are arranged in an array and wired to form an arbitrary logic circuit, The MO3F forming the basic gate under the wiring layer
This is achieved by providing a semiconductor device characterized in that the gate metal of the ET is arranged in an extended manner.

(6,) Examples of the invention An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 5 shows a semiconductor device according to the present invention, and an extended gate metal 2', which is an extension of the gate metal 2 connected to the gate of the MOSFET, is placed under the wiring area A of the first layer, which is a channel between the basic cells 1. The cast has been decided. In the figure, the arrangement of basic cells 1 forming two columns is as follows:
The bases 13 are arranged in an array so as to be shifted by approximately 2 on each side of the cell 1. The extension gate metal 2' under the first layer wiring is perpendicular to the direction of the two rows of basic cells 1, and the shape is lock-shaped from the left row, lock-like from the right row, and left It extends in a straight line from the column, and in a straight line from the right column. As a result, the extension gate metals are arranged at a predetermined distance so as not to be connected to each other. This extended gate metal 2' covers the first layer wiring area and can be used for connection with the first layer wiring.

FIG. 6 is a partial configuration diagram showing gate metal wiring in another embodiment of the present invention.

In the figure, the gate metal 3 extends to the center of the channel area A, which is the first layer wiring between two rows of basic cells 1, and has a structure in which the tips of the gate metal 3 are close to each other. . That is, the length of the gate metal 3 extending from the basic cell 1 is approximately the width of the channel region.

FIG. 6 shows different basic cells 1 arranged in different shapes and lengths of the gate metals 3. Therefore, logic gates suitable for each can be constructed by the arrangement of metal gates shown in FIGS. 5 and 14-6.

FIG. 7 shows another embodiment according to the present invention.
The length extended from the basic cell 1 is approximately the channel region width A, which is shorter than the width A of the basic cell 1. In FIG. 7, the area of the gate metal 40 is small, the gate capacitance is not increased, and the high frequency characteristics are not deteriorated.

FIG. 8 is an enlarged view of a wiring pattern formed using gate metal wiring according to the present invention.

In FIG. 8, the gate metal of the present invention and the first layer wiring applied in the channel region and the metal 5 (2' in FIG. 5) shown by the broken line of the basic cell 1 are represented by Q marks. Connections are made through contact holes 6. That is, conventionally, in the channel region, the first layer wiring and the gate metal of the basic cell 1 were connected to the second layer wiring through a contact hole, but by using the gate metal wiring structure of the present invention, There is no need to use the second layer wiring from the contact hole 6 marked with the mark to the gate metal of the base cell 1. Therefore, since the number of second-layer wiring is reduced, there is no need to increase the number of basic cells 1 and increase the area for second-layer wiring in order to increase the scale, making it easy to create highly integrated LSI chips. It becomes possible. In other words, even if the number of channels for the first layer wiring is increased, the number of channels for the second layer wiring is not increased by the amount of the extended gate metal layer provided below the first layer wiring via an insulator. It's over. The contact hole 7 marked O is the same as the contact hole 7 marked 0 in FIG. 4, and connects the first layer and the 2Nth wiring. When performing second layer wiring within a unit cell that constitutes a logic gate 3
For example, using the array of basic cells 1, a large-scale unit cell such as ALU (Arithmetic an
d Logic 1Jnit) etc. is configured with several tens of basic cells 1, the 2Nth wiring in the liquid unit cell becomes long and the propagation delay time becomes long. However, if the gate metal of the present invention is arranged, the above-mentioned 2 unit cells
By constructing the basic cells 1 in stages, the wiring can be shortened, and the wiring between each stage of the basic cells 1 can be performed using metal gates and first-layer wiring without using second-layer wiring, so that large-scale unit cells can be This can be realized without reducing the number of possible wires of the LSI chip and without increasing the propagation delay time due to the wires. The basic cell is enhancement MOS F.
An EZD type logic gate consisting of a combination of an ET and a depletion MO3FET or other logic gates may also be used.

Further, the extension gate metal may be formed to overlap the second layer wiring, and the extension gate metal and the 2Nth wiring layer may be connected.

(7) Effects of the Invention According to the present invention, by extending the gate metal from the basic cell, the gate of the basic cell can be connected to the first layer wiring in the adjacent channel region without using the second layer wiring. Because you can.

More of the second-layer wiring area can be used for wiring between unit numbers, and not only can the wiring area be used more effectively, but the burden on the router can also be reduced. In the semiconductor device of the present invention, the second layer wiring is a large-scale gate array, i! Even if a unit cell is configured with a gate metal, it is efficiently wired using the gate metal.
There is a great effect of achieving high integration.

Furthermore, since high integration is possible, large-scale integration can be achieved without increasing the chip area. Furthermore, the above-mentioned high wiring efficiency also means that it can be made smaller than conventional LSI chips with the same functions.

[Brief explanation of the drawing]

Figure 1 (a), (bl, fC) shows the conventional MOS F
ET arrangement and gate metal pattern, Figure 2 (al
), (bl), (cl), (cll) are shown in Figure 2 (
al, (bl, (cl, (dl)). Figure 3 is a schematic diagram of a conventional CMOS gate array type LSI chip. Figure 4 is a wiring pattern diagram of a conventional gate array type LSI. Figure 5 6 is a block diagram showing a gate metal according to an embodiment of the present invention. FIG. 6 is a block diagram showing a gate metal according to another embodiment of the present invention. FIG. 7 is a diagram showing a gate metal according to another embodiment of the present invention. FIG. 8 is a diagram of a wiring pattern in which the gate metal of the present invention is used for the wiring shown in FIG. 4. UC: Unit cell Ilo: Number of people = 18 - Power circuit P...Bad 1...Basic cell (BC) 2,3゜4.5...Gate metal 2'...Extension gate metal
6.7...Contact Hole Patent Applicant Fujitsu Limited 19-1 Blind'# O× 3. Relationship with the case of the person making the amendment Patent applicant address: 1015 Niodanaka, Nakahara-ku, Yozaki City, Kanagawa Prefecture (
522) Name Fujitsu Ltd. 4, Agent Address 1015-7 Ogawa Naka, Yozaki City, Kanagawa Prefecture, Subject of amendment Detailed description of the invention column ra>VJ, Brief description of the drawings Column 8, Contents of the amendment As shown in the attached sheet (11) "Figure 2 (al), (bl), ...... It is a logic gate circuit.''Z Correct as follows. [Figure 2 (el, (f), fgl, (hl
are the logic gate circuit diagrams corresponding to each of FIG. 2 (a), (b), (cl.
(2) "Figure 2 (al
, (corrected to bl J Y "Figure 2 (a)". (3) [Drain D
s -1yx "Drain D, correct to -1. (4) "Fig. 2 fbl,
(t) +) is corrected to ``in Figure 2 (bl)''. (5) The ``FET Tr
Drain of e J Y r Source of FET Tra”. (6) “Figure 2 (cl.
(Corrected to "Figure 2 (C)".) [2nd page] written in lines 10-11 of the same page as (6) above
7. Shown in Figure (a). : Use BCY twice, -1vr first
Using two basic cells BCY shown in figure (a),
Correct to. (8) [The above FET described in line 14 of the same page as (6) above]
Tr, -12-. a [The above FET Tr(,, Trot +Tr+a +Tr14 described in lines 18 to 19 of the same page as (6) above)
j 'pt 'The FETTri + T'r121
Tr+. , TrllJ.翰 As stated in lines 4 to 6 on page 11 of the specification of the present application, "units U and C consist of a plurality of basic cells Be" and "here, a unit cell UC consists of a plurality of basic cells BC. 003 Specification No. 1 of the present application
1 Figure 2 (a+), (bt
) , . . . Corresponding circuit diagram” Please correct as below. [Figure 2 (al, (b), (c), (di)
are logic gate pattern diagrams constructed using the basic gate Y in FIG. 1(a), FIG. 2 is a logic gate pattern diagram, and FIG.
(g), fh) are shown in Figure 2 1a), (b), (
cl. Logic gate circuit diagram corresponding to (d)" a4J Figure 2 of the present specification (al, (bl, (
cl, (di Y Correct according to the attached attached sheet. Ru0 Cod 2 Figure (h) VCC Riu C ""4'84 + r (D4

Claims (5)

[Claims] (1) In a semiconductor device in which basic cells consisting of MOSFETs are arranged in an array and wired to form an arbitrary logic circuit, the MO3FETs forming the basic cells are placed under the first wiring layer. A semiconductor device characterized in that a gate metal is arranged in an extended manner. (2) The semiconductor device according to claim 1, wherein a gate metal is extended from the basic cell to a channel region adjacent to the basic cell and connected to a first-layer or second-layer wiring. (3) The basic cells are arranged in parallel, and a channel portion forming a wiring area of the first wiring layer is provided between the rows of the basic cells, and the basic cells provided across the channel portion are mutually arranged. The semiconductor according to claim 1, wherein the gate metals are provided at shifted positions, and the gate metals are provided so as to alternately cross each other in a key shape or a straight shape from the basic cells on both sides of the channel portion. Device. (4) The basic cells are arranged in parallel, a channel portion forming a wiring region of the first wiring layer is provided between the rows of the basic gates, and the metal gates are arranged on both sides of the channel portion. 2. The semiconductor device according to claim 1, wherein the semiconductor device is provided facing each other so that their tips are closer to each other than the basic cells. (5) The basic cells are arranged in parallel, a channel portion forming a wiring region of the first wiring layer is provided between the rows of the basic cells, and the metal gate is located on both sides of the channel portion. 2. The semiconductor device according to claim 1, wherein the semiconductor device extends from the basic cell by a length shorter than 2 of the width of the basic cell.